713 Jobs
Operation Management, Senior Manager (MD Department) [Japanese Speaker]ID:60103
10,000 MYR ~ 15,000 MYROther Selangor DistrictJob Description
• Assist MD to oversee overall operation including sales, accounting, HR, purchasing, maintenance and etc.• Communicate with Japan head quarter office for business guidance, instruction and information sharing.• Accountable for the business revenue and the entire business operations in relation to customer continuity.• Enhance operational excellence and delivering absolute customer satisfaction and people development.• Manage overall business operations of company including engineering, supply chain and other support enabling functions such as HR, accounting to strive for optimum business performance and financial contribution.• Answerable to the business owner in term of business improvement.• Support the needs of the operations team for the business operations.• Develop and implement Company’s strategies and business plans.
Benefit
◆ AL
> 14d 2~5y
> 16d >5y
> 21d >10y
◆ Transport allowance, based on distance (one way)
0 km - <5 km: 2.40
5 km - <15 km: 3.20
15 km - <25 km: 4.20
25 km - <35 km: 5.50
◆ Increment upon confirmation – based on individual’s merit.
◆ Annual Increment – based on individual’s merit.
◆ Annual Bonus – based on individual employee’s performance and company’s profit.
Average 1 month, not more than 4 month’s salary based.
＊＊Attendance record will also influence bonus amount. Prorated Bonus for service between 3 months (subject to confirmed in appointment) to less than a year.
◆ Medical coverage of RM1,500 per year, hospitalization case by case.
◆ Group Accidental insurance coverage.
◆ Company trip/outing will be once in every two years depending on employees’ performance and company’s profit
◆ Company eat-out at an interval that varies from year to year depending on employees’ performance and company’s profit.
◆ Liabilities: EPF, SOCSO, EIS & HRDF LEVI (standard requirement)Special Project OfficerID:60097
3,500 MYR ~ 5,000 MYRShah AlamJob Description
SummaryBusiness Development and Personal Assistant role supporting the Director in client management, strategic business initiatives, and daily business operations. Responsible for business development activities, market research, client coordination, and supporting sales and partnership opportunities.Job Responsibilities• Executive Support: Provide comprehensive assistance to Director managing day to-day business requirements and ensuring seamless coordination of high-priority tasks.• Client Engagement: Accompany the CEO to meetings with key stakeholders and corporate clients; assist in preparing presentations and follow-up communications.• Business Development: Support the initial stages of the sales cycle, including lead identification, market research, and client relationship management.• Nationwide Travel: Travel across Malaysia as required to support project site visits, client negotiations, and business events.• Communication Bridge: Act as a professional liaison between the CEO’s office and internal/external parties.
Benefit
phone allowance : Yes
petrol allowance: yes
commission : follow comp scheme
employee insurance : After confirm
Annual leave : 14days
Sick leave : 14daysWarehouse SupervisorID:60095
5,000 MYR ~ 7,000 MYRNibong TebalJob Description
• Manage daily warehouse operations including receiving, storage, and issuance of materials• Ensure inventory accuracy and maintain proper stock records in ERP system• Monitor stock levels and coordinate with Purchasing / Planning for replenishment• Coordinate closely with Production team to ensure timely material supply• Perform stock count / cycle count and investigate discrepancies• Ensure proper labeling, FIFO practice, and material traceability• Supervise and guide warehouse assistants / operators (if applicable)• Maintain warehouse cleanliness, safety, and 6S standards• Handle incoming & outgoing shipments, including documentation• Liaise with logistics providers for delivery arrangement
Benefit
- Annual Leave 10 days
- Medical Leave 14 days
- Meal Allowance
- Yearly Bonus
- Salary Increment
- Medical Benefit and Insurance
- Maternity and Paternity LeaveService Quality Senior Executive/Assistant ManagerID:60089
6,000 MYR ~ 8,000 MYRPutrajaya/Cyberjaya, Other Selangor DistrictJob Description
Quality Improvement Program & Initiative 1. To organize and coordinate the Service Quality Standard training to all new frontliners in order to improve their knowledge and understanding.2. To assist and support all current and new improvement programs/strategies.3. To coordinate with respective stakeholders.4. To monitor and analyze the results of the implemented action plans for continuous improvement.Audit & Assessment1. To conduct service quality audits and assessments on the quality management system & service quality standard to assess compliance, identify areas for improvement and identify undocumented good practices with the aim to standardize such practices across the GroupCustomer Satisfaction Survey & Feedback1. To assist to conduct periodic Customer Satisfaction Survey or other methods to obtain customer’s feedback. Analyze and report on customer’s feedback in order to recommend areas for improvement and to ensure improvements made are effective in meeting the company’s objectives. Support to Business & Supporting Units1. To assist in compiling data and information for reports ie KPI, Customer Feedback and Complaint Report & Support System. 2. To jointly develop effective corrective and preventive measures.3. To attend compliance and certification audits to provide clarification and assistance.
Benefit
- Annual Leave 19 days
- Medical Leave
- Travel Allowance
- Medical Claims
- Optical/Dental Claims
- Medical Insurance
- Performance Bonus
- Yearly IncrementLogic Design Verification EngineerID:60088
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking to hire Logic Verification Engineer. Familiarity with LPDDR and HBM memory interface IP will be a plus. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain UVM-based verification environments for various IPs, including constrained-random testbenches, protocol-aware monitors, scoreboards, and checkers.• Author detailed verification plans based on specifications, architectural documents, and use-case scenarios; own coverage closure end-to-end.• Drive coverage-driven verification (CDV): functional coverage (covergroups/coverpoints), code coverage (statement, branch, toggle), and SystemVerilog assertions (SVA); identify gaps and close with targeted test scenarios.• Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis; apply Formal Property Verification (FPV) to prove critical design properties.• Debug simulation failures in collaboration with RTL designers; document results, coverage metrics, and regression summaries for traceability and sign-off.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDFT Logic Design EngineerID:60087
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a DFT Logic Design Engineer to implement testability infrastructure across our digital IP portfolio. You will define DFT strategy, integrate scan and BIST structures at the RTL level, and drive fault coverage from early design through silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Define and own the DFT architecture for digital and mixed-signal blocks: scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, and MBIST/LBIST planning; document and maintain the DFT specification throughout the design cycle.• Develop and integrate DFT RTL (SystemVerilog/Verilog): scan wrappers, BIST controllers, test access ports, and clock/reset control logic; ensure DFT structures are synthesis-clean, timing-closed, and do not degrade functional performance or power.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets; achieve and sign off on target fault coverage metrics agreed with the test engineering team.• Collaborate with RTL designers on DFT-aware coding guidelines; perform DFT rule checking, CDC analysis, and Lint to identify and resolve testability violations early in the design cycle before netlist handoff.• Support physical design handoff: provide scan chain ordering recommendations, validate DFT netlist post-layout (LEC, STA), and resolve DFT-related ECOs during timing closure and tapeout.• Support post-silicon validation and ATE bring-up: work with test engineers to load and debug ATPG patterns on ATE platforms, analyze yield data, and triage failing patterns back to root-cause RTL or physical design issues.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout Designer/LeadID:60085
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Designer to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Library Layout Designer/LeadID:60084
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Designer to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom Layout Designer/LeadID:60083
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking an Custom Layout Designer to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDesign Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment