Design Automation Engineer (Standard Cells Library)ID:60082

8,000 MYR ~ 16,000 MYRBayan Lepasabout 9 hours ago

Overview

  • Salary

    8,000 MYR ~ 16,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.

    Key Responsibilities
    • Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.
    • Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.
    • Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.
    • Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.
    • Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.
    • Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.

Qualifications

  • Requirement

    • BS/MS in Electrical/Electronic Engineering, Computer Engineering, or equivalent experience.
    • 3–5 years of hands-on experience in a standard cell library, custom IP, or characterization/CAD environment.
    • Working experience running a characterization tool such as Cadence Liberate or Synopsys PrimeLib (or equivalent): able to set up configuration files, submit runs, debug failed jobs, and interpret log output.
    • Practical understanding of standard cell Liberty models: NLDM/CCS timing arcs, power models, and variation-aware formats (LVF/POCV) at a consumer level (i.e. how characterization produces them, not full methodology ownership).
    • Solid SPICE-level knowledge: able to read a SPICE netlist, understand measure statements, and debug a failing simulation with a circuit designer. Familiarity with HSPICE or Spectre as the underlying engine.
    • Strong scripting in Python and Tcl for flow automation, data parsing, and regression reporting. Working proficiency in Cadence SKILL for testbench and Pcell-related automation.
    • Comfortable on Linux with shell scripting and cluster job submission; basic Makefile / build-system literacy.
    • Experience with version control and working in a shared release environment with defined directory conventions.

    Preferred / Nice-to-Have Experience
    • Exposure to statistical / variation-aware characterization (Monte Carlo, sensitivity-based flows, LVF generation).
    • Familiarity with STA tools (PrimeTime or Tempus) as a downstream consumer of the libraries, sufficient to reproduce and hand off miscorrelation cases raised by the design team.
    • Exposure to library release management: manifest generation, checksum / sign-off documentation, and multi-view consistency checks (Liberty vs. LEF vs. GDS).

  • English Level

    -

  • Other Language

    English

Additional Information

Related Jobs