34 Jobs: Job Vacancies for Other(IT/Internet/Telecommunications) Engineer Positions
Web Developer (Marketing Content Development and SEO Implementation)ID:60470
4,000 MYR ~ 7,000 MYRKota Damansara/Petaling JayaJob Description
■ ROLE SUMMARYWe are hiring a Web Developer to work cross-functionally with:- Marketing (traffic & visibility)- Sales (conversion & objections)- Product (positioning & packaging)Your job is not just to build pages, but to build revenue infrastructure■ CORE RESPONSIBILITIES1. Marketing Support – Visibility & SEO ExecutionYou will implement and maintain all SEO and structural improvements:・Build SEO-optimized landing pages in Thrive Architect (WordPress)・Implement structured 5W1H content sections・Build FAQ and comparison blocks・Improve internal linking structure・Implement breadcrumbs and crawlable navigation・Ensure dropdown menus use HTML/CSS (not JS-dependent)・Improve blog categorization and pillar structure・Add article-type labels and filtering・Implement structured data (Schema / JSON-LD)・Maintain sitemap and indexing health・Ensure GPTBot and AI crawlers are not blocked・Improve Core Web Vitals and page speedYou are responsible for making strategy executable.2. Sales Support – High-Converting Sales PagesYou will work directly with the Sales Team to:・Build full sales pages for courses and programs・Design objection-handling sections・Build comparison tables (Program vs Self-Learning)・Build FAQ sections based on real sales objections・Implement testimonial sections strategically・Improve clarity and scannability・Optimize CTA placement and page flowYou must understand:・Problem agitation・Objection handling・Urgency mechanics・Information hierarchy・Above-the-fold conversion strategy・We are not looking for pretty pages.We are looking for pages that convert qualified prospects.3. Product Team Support – Product Positioning & Page ArchitectureYou will work with Product to:・Design product pages for new programs・Structure category pages (Foundation / Advanced / Mastery)・Create modular page templates for new course launches・Improve clarity of program pathways・Build upgrade / cross-sell structures・Design package breakdown pages clearlyYou will help translate product complexity into structured, clear pages.If a product is confusing online, that is a structural failure.4. Conversion Rate Optimization (CRO)・Implement A/B tests (headlines, CTA positions, layout blocks)・Improve mobile conversion experience・Optimize long-form pages for readability・Reduce drop-offs on key pages・Improve loading speed on high-traffic pages・Improve WhatsApp click-through sections5. E-E-A-T & Authority Implementation・Build and maintain author pages for trainers, Expertise page & Testimonial page・Implement internal linking from blogs to trainers, LinkedIn profile linking・Ensure structured author markup・Maintain authority signals across the site6. Ongoing Technical Maintenance・Monitor Google Search Console・Fix crawl errors・Maintain indexing health・Improve site performance・Coordinate with external SEO vendors when required
Benefit
・Basic Salary = RM 4,000 ~ RM 7,000
・Life and Medical Insurance
・Medical, Dental and Optical Claims
・Parking Allowance
・Gym membership subsidy
・Discounted access to all our investing and trading education programsUI/UX DesignerID:60650
7,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
We are seeking a talented and detail-oriented UI/UX Designer with a keen aesthetic sense and strong logical thinking to join our growing product team. You will take full ownership of the app design lifecycle — from initial visual concepts through to final delivery — while working closely with our React Native Front-End Developers to bring the product to life.This is not just a visual design role. We are looking for someone who approaches design with a development mindset — someone whose Figma files are clean, structured, and built to accelerate front-end implementation.• Own the end-to-end design process independently — from UX research and wireframing to high-fidelity UI and developer handoff• Design intuitive and visually compelling mobile app interfaces for both iOS and Android platforms• Create and maintain a scalable design system using Figma components, variables, and auto layout• Design data visualisation screens including charts, scores, and progress indicators• Develop gamification elements such as badges, streaks, rewards, and celebration moments• Produce detailed interaction specifications and animation guidelines for engineers• Conduct user research and translate findings into actionable design decisions• Collaborate closely with React Native developers to ensure designs are feasible, consistent, and implementation-ready• Ensure all designs adhere to Apple's Human Interface Guidelines and Google's Material Design 3 standards
Benefit
Salary range: ~RM7,000 - RM9,000
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesDesign Manager / Design CoordinatorID:60649
10,000 MYR ~ 20,000 MYRBayan LepasJob Description
- Lead and coordinate the project engineering team for project design from programming to IFC design.- Organize routine client and internal engineering team coordination meetings, develop meeting minutes, track ARs, and monitor close-out activities.- Ensure overall project design work follows the company's project execution standards, client requirements and specifications, local compulsory codes, and other applicable regulations.- Organize internal and client project design reviews, and track and monitor the close-out of review comments.- Coordinate and manage discipline/work package interfaces.- Maintain project design change procedures, develop design change logs, and track design changes.- Monitor the overall project design schedule and implement mitigation actions when necessary.- Coordinate with other project stakeholders.- Perform other project design coordination and management tasks.
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementFrontend EngineerID:60588
7,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
• Build and maintain mobile application features using Flutter and Dart for both Android and iOS, with state management solution• Translate UI/UX designs from Figma into responsive, pixel-accurate Flutter screens, accurately implementing interaction specs and animation guidelines provided by the UI/UX Designer• Collaborate closely with the UI/UX Designer by attending design reviews, providing technical feasibility input, and bridging the gap between design intent and technical execution• Implement high-quality animations and micro-interactions• Integrate RESTful APIs provided by the Backend Engineer, handling data fetching, error states, and loading experiences to ensure a seamless end-user experience• Write clean, readable, and testable code following established coding standards and best practices• Debug and resolve issues across Android and iOS, including platform-specific quirks and rendering inconsistencies• Prepare and maintain release builds for both the Google Play Store and Apple App Store• Proficiency in version control using Git — including branching strategies, pull requests, and code reviews via platforms such as GitHub• Take ownership of testing by independently identifying, reproducing, and resolving bugs across Android and iOS
Benefit
Salary range: ~RM7,000 - RM9,000
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesE-Commerce Platform SupervisorID:60603
6,000 MYR ~ 12,000 MYRBangsarJob Description
- Liaise and maintain strong relationships with e‑commerce platform owners.- Monitor and manage overall service quality across assigned platforms.- Conduct data reviews and prepare business performance reports.- Coordinate and collaborate effectively with cross‑functional teams.- Independently plan and execute initiatives to meet customer requirements.- Lead and develop a high‑efficiency team.
Benefit
- Annual Leave: Start from 13 days
- Medical Leave: Start from 14 days
- Panel Clinic
- Miscellaneous allowance (attendance, transport etc.)
- Yearly increment
- Performance bonus
- Sports (e.g. Gym)
- Teambuilding
- Marriage leave
- Paternity and maternity leave
- Compassionate leaveBackend EngineerID:60573
7,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
• Design and develop scalable backend systems and RESTful APIs.• Build and maintain server-side application logic.• Integrate with databases, third-party services, and external systems.• Optimize system performance, scalability, and security.• Design and maintain database schemas and ensure data integrity.• Troubleshoot and resolve backend-related issues in development and production environments.• Participate in system architecture design and technical documentation.• Collaborate with frontend developers, system analysts, and cross-functional teams.• Mentor junior developers and conduct code reviews to maintain coding standards.
Benefit
Salary range: ~RM7,000 - RM9,000
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
