DFT Logic Design EngineerID:60087

8,000 MYR ~ 16,000 MYRBayan Lepasabout 3 hours ago

Overview

  • Salary

    8,000 MYR ~ 16,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking a DFT Logic Design Engineer to implement testability infrastructure across our digital IP portfolio. You will define DFT strategy, integrate scan and BIST structures at the RTL level, and drive fault coverage from early design through silicon bring-up. Seniority level to be determined by experience.

    Key Responsibilities
    • Define and own the DFT architecture for digital and mixed-signal blocks: scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, and MBIST/LBIST planning; document and maintain the DFT specification throughout the design cycle.
    • Develop and integrate DFT RTL (SystemVerilog/Verilog): scan wrappers, BIST controllers, test access ports, and clock/reset control logic; ensure DFT structures are synthesis-clean, timing-closed, and do not degrade functional performance or power.
    • Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets; achieve and sign off on target fault coverage metrics agreed with the test engineering team.
    • Collaborate with RTL designers on DFT-aware coding guidelines; perform DFT rule checking, CDC analysis, and Lint to identify and resolve testability violations early in the design cycle before netlist handoff.
    • Support physical design handoff: provide scan chain ordering recommendations, validate DFT netlist post-layout (LEC, STA), and resolve DFT-related ECOs during timing closure and tapeout.
    • Support post-silicon validation and ATE bring-up: work with test engineers to load and debug ATPG patterns on ATE platforms, analyze yield data, and triage failing patterns back to root-cause RTL or physical design issues.

Qualifications

  • Requirement

    • BS/MS in Electrical/Electronics Engineering, Computer Engineering, or related field.
    • 3~5+ years of hands-on DFT experience in a digital ASIC or SoC environment, with demonstrable ownership of scan insertion, ATPG, and fault coverage sign-off on at least one taped-out design.
    • Solid RTL coding skills in SystemVerilog/Verilog; ability to read, write, and review DFT RTL (scan wrappers, BIST controllers, TAP logic) and identify DFT violations at the source level.
    • Proficiency with industry DFT and ATPG tools: Synopsys DFT Compiler / TetraMAX, Tessent ATPG/Scan/MBIST or Cadence Encounter Test / Modus; working knowledge of synthesis (Design Compiler or Genus) and static timing (PrimeTime or Tempus).
    • Familiarity with IEEE 1149.1 (JTAG), IEEE 1500 (core test), and scan compression techniques (X-Bounding, EDT/Staggered); understanding of fault models including stuck-at, transition delay, and cell-aware.
    • Strong scripting ability in Tcl and Python for flow automation; experience with CDC/Lint tools (Spyglass or equivalent) and version-controlled RTL environments (Git/Perforce).

    Preferred / Nice-to-Have Experience
    • Familiarity with LPDDR or HBM memory interface architecture; understanding of PHY-controller partitioning and the testability challenges unique to high-speed memory interfaces (loopback modes, BIST for DQ/DQS paths, ZQ calibration test hooks).
    • Experience with IEEE 1687 (iJTAG) for embedded instrument access and hierarchical DFT on multi-die or chiplet-based designs.
    • Exposure to advanced-node (7 nm and below) DFT challenges: cell-aware ATPG, at-speed testing, process variation-aware pattern generation, and low-capture power scan techniques.
    • Prior experience contributing to DFT methodology definition in a startup or new team environment; comfort establishing flows and documentation from scratch with minimal existing infrastructure.

  • English Level

    -

  • Other Language

    English

Additional Information

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