46个职位: 峇央峇鲁 Bayan Baru最新招聘信息
Custom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Analog Mixed-Signal Design)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Highspeed IO Buffer LPDDR6)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Software Engineer (PLC) ID:60017
6,000 MYR ~ 8,500 MYRBayan Baru工作内容
• Design, development, and implementation of PLC and/or PC based software solutions• Perform system integration, testing and commissioning of advanced control systems for equipment automation system.• Participate in control system requirement analysis.• Involved in drafting of functional specifications and detailed design specification.• Provide technical onsite support to external and internal customers.• Interpret client requirements, identify design parameters, and ensure solutions are implemented accurately and within budget to meet project requirements and schedules• Ensure software issues are resolved in a timely manner
福利制度
Salary package: ~RM5,000 - RM7,000
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview sessionSenior Mechanical Design EngineerID:60011
5,000 MYR ~ 8,000 MYRBayan Baru工作内容
• Conduct equipment design & development work according to customers and internal specifications.• Act as project lead to plan, organize and co-ordinate their respective project’s meetings to review design and ensure projectsare kept to schedule.• Maintain and control relevant documents related to R & D activities per requirements.• Maintain, keep track, and ensure Billed Materials is updated.• Generate detailed 2D/3D drawings• Raise ECN for update of changes to design and drawings and follow up on approval and ECN flow.• Provide technical support to process & production, supply chain & QA for review and troubleshooting of design and drawings
福利制度
Salary package: ~RM5,000 - RM7,000
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview session(WFH-PENANG) Account Manager (Semiconductor) ID:60008
8,000 MYR ~ 10,000 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya, Butterworth, Bukit Mertajam, Simpang Ampat, Juru, Nibong Tebal, Bukit Minyak, Batu Kawan工作内容
A leading Japanese manufacturer of high-reliability test sockets & burn-in solutions, is expanding in Penang. We’re looking for a results-driven Account Manager to grow our business in the region.What You’ll Do• Drive new business opportunities while managing key accounts• Identify and develop new projects within semiconductor customers (MNCs & OSATs - Outsourced Semiconductor Assembly and Test)• Engage customers on both technical and commercial discussions• Prepare quotations, follow up, and close deals• Build strong relationships with engineers, buyers, and decision-makers• Track pipeline, market trends, and competitor activity
福利制度
- Performance Bonus
- Annual Leave: 8–16 days per year, depending on how long the employee has worked with the same employer as per Msian Employment Act
- Public Holiday : As per gazetted public holidays in Malaysia.
- Fixed car allowance
- Phone allowance
- Full claimable expensesSIPI Engineer (Senior/Staff/Principal)ID:59941
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Job SummaryResponsible for Signal Integrity and Power Integrity (SI/PI) analysis, simulation, lab validation, and customer support for high-speed digital interfaces across chip, package, and board levels.Key ResponsibilitiesSignal Integrity• Simulation for high-speed interfaces: HBM, DDR, LPDDR, UCIe, MIPI• Crosstalk, reflection, impedance, and eye-diagram analysis• Transmission line modeling and stackup reviewPower Integrity• Power delivery network (PDN) analysis and optimization• Decoupling capacitor selection and validation• PDN impedance measurement and simulation correlationTools & Methods• SI/PI tools: HyperLynx, Ansys SIwave, Cadence Sigrity• Lab equipment: TDR, VNA, high-speed oscilloscope• S-parameter, Y/Z-parameter and multi-port matrix analysis Collaboration• Work with chip, package, PCB design, and layout teams• Support customers on board design reviews and technical queries• Participate in design reviews, failure analysis, and root-cause debugging
福利制度
- Annual Leave 14 days
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementProject Manager(Penang)ID:59932
10,000 MYR ~ 15,000 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya工作内容
SummaryA construction project manager responsible for planning, scheduling, cost, quality, and safety management, coordinating with site teams, engineers, and subcontractors to ensure smooth execution and maintain As-built documentation.Key Responsibilities- Manage overall project planning, scheduling, quality, cost, and safety for construction projects.- Coordinate with site teams, design engineers, and subcontractors to ensure smooth project execution.- Review and approve construction drawings and design documents to ensure accurate implementation of design intent.- Oversee progress monitoring, budget control, and procurement of materials.- Ensure compliance with Safety, Health, and Environment (SHE) standards and implement risk management measures.- Analyze issues that arise during construction and propose and implement corrective actions.- Maintain and update As-built drawings and related documentation upon project completion.
福利制度
- Annual leave: 10 days
- Medical leave: 14 days
- Medical claims: RM1,000/year
- Accommodation
- OT allowance
- Performance appraisal twice yearly.
Mid year - Increment & promotion
Year end - bonus.Emulation and Prototyping Engineer (Senior/Lead)ID:59881
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a highly skilled and motivated Senior or Lead Emulation and Prototyping Engineer to define and lead emulation strategies for IP, complex SoC and system-level projects. This role requires a strong technical leader who can work independently, while also collaborating closely with system architects and pre-silicon verification teams to drive successful pre-silicon validation, firmware development, and early software enablement using industry-leading emulation/prototyping platforms.Key Responsibilities:• Define and lead the emulation and prototyping strategy for IP & SoC programs to support architectural validation, functional verification, and software bring-up.• Work closely with chip architects to understand IP & system-level design goals and translate them into emulation requirements and constraints.• Collaborate with pre-silicon design verification engineers to integrate emulation/prototyping into the broader verification strategy and identify high-value use cases.• Partition and map RTL designs to commercial emulation/prototyping platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce).• Develop emulation models, transactors, and hybrid environments (e.g., simulation + emulation or virtual platforms).• Lead bring-up and debug activities of the emulation/prototyping environment, ensuring performance, accuracy, and reusability.• Drive the development of automated test environments, infrastructure, and scripts to enable fast deployment and repeatability.• Support firmware and software teams with stable and functional pre-silicon platforms for development and debug.• Maintain comprehensive documentation including emulation and prototyping setup guides, debug workflows, and system usage instructions.• Mentor junior engineers and evangelize emulation best practices across engineering teams.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment