46个职位: 峇央峇鲁 Bayan Baru最新招聘信息
Business Development Manager (Janitorial Services)ID:60616
10,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru工作内容
The Business Development Manager is responsible for driving business growth by securing new contracts, managing key customer relationships, identifying market opportunities, and developing competitive commercial proposals for Janitorial, Cleanroom Cleaning, Technical Cleaning, and Support Services. The role requires close collaboration with Operations, Finance, Procurement, HR, and HSEteams to ensure successful tender submissions, project implementation, and long-term customer satisfaction.Business Development & Sales- Identify and develop new business opportunities within manufacturing, semiconductor, data centre, and industrial sectors.- Generate sales leads through networking, customer visits, referrals, industry events, and market intelligence.- Build and maintain a strong sales pipeline to achieve monthly and annual revenue targets.- Develop strategic account plans to expand existing customer portfolios.Tender & Proposal Management- Lead the preparation of RFQ, RFP and tender submissions.- Review customer Scope of Work (SOW) and identify commercial and operational requirements.- Coordinate with Operations, HR, Procurement and Finance in preparing costing, manpower deployment, equipment proposals, organisation charts, method statements, risk assessments and presentations.- Ensure submissions are complete and submitted within deadlines.Customer Relationship Management- Establish and maintain strong relationships with customers.- Conduct business review meetings and identify service expansion opportunities.- Manage contract renewals and ensure high customer satisfaction.Commercial & Pricing Strategy- Develop competitive pricing strategies while maintaining profitability.- Negotiate commercial terms and service agreements.Market Intelligence- Monitor industry trends, competitors and emerging opportunities.- Recommend new service offerings and business strategies.Project Transition Support- Support project mobilisation and coordinate with HR and Operations during implementation.Internal Collaboration- Work closely with Operations, HR, Finance, Procurement, HSE and Quality Assurance.Reporting- Prepare weekly/monthly sales reports, pipeline forecasts and management.
福利制度
- AL: Starting from
- MC: Starting from 14 days
- EPS, SOCSO
- Allowance: TBC
- Performance Bonus
- Medical Benefits & InsuranceSales ManagerID:60239
8,000 MYR ~ 10,000 MYRBayan Baru工作内容
- Promotes product sales (semiconductors: MCU, ASIC, ASSP and Flash)- Foster strong relationship with our customers and our distributors- Gather market information and updates such as pricing, competitors’ activities, production, demand trends, newcustomers’ entries, current customer’s situations.- Provides monthly demand forecasts- Coordinates with internal departments to ensure that prompt deliveries and general good services are provided for customers- Assists in handling rejects complaints by mediating between customers and marketing department- Assists in payment collection- Assist in other promotional activities such as exhibitions and seminars- Source for new business opportunities★Main Focus: Existing client support (Account Management).★Client Base: 10 companies located in Malaysia and Indonesia.★Business Trips: To KL: 2–3 times a year.To Indonesia: 1–2 times a year.★Language SkillsMust-Have: English and Malay (including Indonesian language proficiency).Nice-to-Have: Japanese proficiency is highly preferred.Note on Mandarin: Mandarin is preferred as some communication in Chinese may occur, but it is not a must-have. Prioritize relevant sales experience over Mandarin skills.
福利制度
1. Allowances & Expense Reimbursements
Medical & Dental: Max RM 400 (Medical) / RM 200 (Dental) per year (Claim by receipt, paid monthly).
Car & Travel: Fixed Car Allowance RM 1,400/month.
Petrol (Max RM 600/mo), Tolls (Max RM 300/mo), Mileage (RM 0.60/km).
Mobile & Parking: Full reimbursement for monthly phone bills & parking.
Client Entertainment: Fully claimable with receipts.
Business Trips: Air tickets provided. Travel allowance applies to overseas trips only.
2. Salary, Bonus & Health Check
Payday: 25th of every month.
Salary Increment: Annual (approx. 1–5%).
Bonus: Annual in April (approx. 3 months for this year).
Health Check: 1 time per year.
3. Leave Policy
Annual Leave:
1–2 yrs: 14 days
Sick Leave: Up to 14 days/year upon confirmation (Medical certificate required).
Hospitalization: Up to 60 days/year (inclusive of sick leave taken).
4. Statutory Contributions
EPF & SOCSO: Processed according to Malaysian regulations via an external accounting firm.Procurement Officer (1-Year Renewable Contract) ID:60486
5,000 MYR ~ 7,000 MYRBayan Baru工作内容
• Actively source, assess and research potential suppliers for machine components, materials and products from both local and overseas supply sources.• Make on-going efforts to identify new suppliers and review current suppliers to maintain a pool of qualified suppliers.• Foster strong supplier relationships and negotiation skills to secure best price, payment terms, lead time and ensure on-time delivery.• Work closely with suppliers on delivery scheduling, quality issues, component specifications and certification requirements.• Assist to arrange trainings with suppliers when required.• Manage, maintain and monitor project costings closely to achieve cost savings.• Manage end-to-end purchase order processes and maintain complete documentation of all orders and related records.• Work closely with internal teams to ensure cost-savings measure and on-time delivery for projects.• Enforce and ensure internal and external compliance to the company’s procurement policies and procedures.• Perform procurement-related duties as assigned.
福利制度
Salary package: ~RM5,000 - RM7,000
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview sessionRegional Development ManagerID:60480
8,000 MYR ~ 10,000 MYRBayan Lepas, Bayan Baru工作内容
- Able to call on semiconductor manufacturer in Automated inspection or Test Department to promote company Automated Optical Inspection and Test solution- Establishing and maintaining strong relationship with existing and new potential customers- Establish strategic action plans to win a deal (prospecting, presentation, technical closure, commercial closure and after-sales follow up)- Prepare Sales visits, maintain customer database and update project status/ activity reports on weekly basis- Develops and executes strategic account plans to achieve sales goal and value-creating objectives
福利制度
- AL: Starting from 14 days
- MC: Starting from 14 days
- EPF, SOCSO, EIS
- Car Allowance RM800
- Extra Travel allowance
- Mobile Expenses claimble
- Travel Expenses Claimable
- Medical Insurance
- Medical Claim after confirmationSales EngineerID:60268
4,000 MYR ~ 8,000 MYRBayan Baru工作内容
We are seeking a Sales Engineer to support the growth of our vision inspection solutions business by working closely with customers, partners, and our Tokyo headquarters. Key Responsibilities- Manage all sales-related activities for vision inspection systems.- Visit factories and machine manufacturers to propose and present our in-house vision inspection solutions.- Respond to customer inquiries, including coordination of delivery schedules and preparation of quotations.- Collaborate with members of the Tokyo headquarters.- Travel within Malaysia, as well as to Singapore and Indonesia, as required.- Depending on individual aptitude and career aspirations, rotation to a Technical Engineer role is possible.
福利制度
- AL: starting from 8 days
- MC: starting from 14 days
- Performance Bonus: Paid twice a year
- All Travel Expenses Reimbursement basis
- Phone allowance
- Company parking
- Extra travel allowance
- Company car provided for outstation
- Medical claim: RM1,200 per yearDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru工作内容
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment