概述

• 薪资

  8,000 MYR ~ 20,000 MYR

• 工作行业

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• 工作内容

  Job Summary
  We are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.
  
  Key Responsibilities
  1. DFT Architecture & Planning
  • Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.
  • Document and maintain DFT specifications throughout the design cycle.
  • Lead the planning and execution of various DFT feature implementation and verification.
  
  2. DFT RTL Design & Integration
  • Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.
  • Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.
  • Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.
  
  3. Scan, ATPG & Verification
  • Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.
  • Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.
  • Perform gate-level simulation (GLS) to verify scan design.
  • Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.
  • Achieve and sign off target fault coverage metrics.
  
  4. Design Quality & Validation
  • Collaborate with RTL designers to establish DFT-aware coding guidelines.
  • Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.
  • Support netlist validation through LEC and STA during implementation and timing closure.
  • Resolve DFT-related ECOs prior to tape-out.
  
  5. JTAG & Boundary Scan
  • Design and verify TAP controllers.
  • Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.
  • Generate BSDL files and support Boundary Scan verification.
  
  6. Post-Silicon & Manufacturing Support
  • Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.
  • Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.
  • Support test pattern bring-up and production test activities.