17个职位: 招聘信息 电路设计
Electrical EngineerID:58357
5,000 MYR ~ 7,000 MYRMont Kiara工作内容
-Assisting in equipment and software installation. -Operating and troubleshooting camera and PLC systems on-site. -Supporting image capturing processes. -Running or modifying simple software programs for image processing tasks. -Collaborate with mechanical and software team to integrate electrical systems into complete machine solutions.-Prepare testing reports, system documentation, and technical manuals for internal and customer use.-Ensure compliance with relevant safety and regulatory standards in all electrical work.-Support project timelines by tracking tasks, reporting progress, and communicating effectively with the team.-Maintaining accurate records of all work completed. -Hands-on skillset in circuit diagrams drawing and machine maintenances is preferable
福利制度
-Employment Type: Full-time
-Probation Period: 6 months
-Working Hours: Mon – Fri 8.00am – 5.15pm
-Working Calendar: Follows the Company calendar
-Working Location: Mont Kiara
-Basic Salary: RM5,000 ~ 7,000 (Subject to experience and skills)
-Performance Bonus: No
-Salary Increment: usually once a year, depend on performance
-Medical Allowance: Medical RM300/ year, Dental RM200/ year
-Company Car: No
-Travel Allowance: Yes
-AL: 14 days – 22 days
-MC: 14 days – 22 days
-Housing Allowance: NoSenior System Board Design EngineerID:58749
10,000 MYR ~ 40,000 MYRBayan Lepas工作内容
• Lead the end-to-end development of complex multilayer system boards, including architecture definition, schematic design & technical decision-making.• Drive component selection, trade-off analysis & architecture optimization to meet electrical, thermal, and mechanical constraints.• Ensure high-speed signal integrity, power integrity & EMI/EMC compliance through simulation, design & testing.• Lead board bring-up, root cause analysis, and system-level debug using lab instruments (oscilloscopes, logic analyzers, spectrum analyzers, etc.).• Define test strategies and validate hardware against functional, environmental, and reliability requirements.• Prepare and review detailed design documentation: schematics, BOMs, layout constraints, test reports, and manufacturing files.• Collaborate with PCB layout engineers on components placements, routing and PCB stack up.• Skilful on handing rework tool to preforming board rework and modifications to hardware components.• Collaborate with cross-functional teams including SoC, firmware, packaging, mechanical, and manufacturing teams.• Interface with suppliers, PCB fabrication and assembly vendors for prototyping and production.• Provide technical leadership, mentoring, and code/design reviews for junior team members.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSMT Engineer (Kulim) ID:58730
8,000 MYR ~ 9,000 MYRKulim工作内容
• Provide manufacturing technical support to the contract manufacturing• Provide the SMT production technical support at client side• Lead and coordinate CM analysis of quality issues; propose corrective actions and follow up on implementation. • Participate in definition and management of process-related parameters and standards• Monitor and audit the Contract Manufacturer process control, record non conformities, review Contract Manufacturer corrective action and track implementation action to confirm final effectiveness. • Lead contract manufacturer process improvements and implement quality enhancement measures and confirm result. • Collaborate with NPI engineers in completing DFM evaluation for new projects. • Research, validate and implementation new manufacturing processes and technologies.
福利制度
Salary: RM8,000 - RM9,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)SMT Programmer (Penang) ID:58723
8,000 MYR ~ 9,000 MYRBayan Lepas工作内容
1. Programming and Setup• Create and Optimize Programs: Develop new placement programs for the Fuji NXT III from CAD data (e.g., centroid data) and Bill of Materials (BOM) using Fuji Nexim.• Program Finetuning: Conduct first-article inspections and troubleshoot new programs on the machine to ensure correct component pickup, placement coordinates, and component recognition settings.• Component Library Management: Create, maintain, and update accurate component part data in the machine's library, including vision recognition settings, part dimensions, and nozzle assignments.• Feeder and Setup Verification: Generate and manage feeder setup sheets. 2. Process Optimization and Improvement• Cycle Time Reduction: Analyze machine performance data and optimize placement sequences and head utilization to achieve the shortest possible cycle times and maximize component per hour (CPH).• Yield Improvement: Monitor and analyze placement defects (e.g., missing, tombstone, misalignment) and implement corrective actions, including program adjustments.• New Product Introduction (NPI): Work to implement new products, focusing on Design for Manufacturability (DFM) reviews related to SMT.3. Machine Operation and Know-How• Troubleshooting: Respond to and resolve machine errors, including component vision failures, machine issues, and communication errors.• Operator Training: Train SMT operators on daily machine operation, material replenishment, minor troubleshooting, and correct changeover procedures.
福利制度
Salary: RM8,000 - RM9,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)Automation & Commissioning Engineer (PLC & HMI)ID:58545
4,470 MYR ~ 4,970 MYRSeri Kembangan工作内容
• Responsible in planning, developing, conducting testing & commissioning for project control system• To design and draw electrical circuits for local control panel for AWCS develop PLC program and HMI software• To design control system architecture and Electrical Schematic Drawings for local control panel for Automated Waste Collection System• To perform factory acceptance test (FAT) and site acceptance test (SAT) and termination schedule• To identify any breakdown and perform troubleshooting or any technical support as necessary required• To conduct testing & commissioning of Company's product and system before handling over to customer
福利制度
• Basic Salary = RM 4,000 ~ RM 4,500
• AL: <2Y 14 days, 2~5Y 16 days, >5Y 18 days
• MC: <2Y 14 days, 2~5Y 18 days, >5Y 22 days
• Car Allowance = RM 350
• Petrol Card: Limit at RM 300
• HP Allowance: Limit RM 120
• Average 3 months performance bonus (based on performance)
• Team Building
• Hari Raya Ramadhan Dinner
• CNY DinnerSenior Staff IP Logic Design / MicroarchitectID:58605
15,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to drive a low power and complex design to completions.2. IP Quality Responsibility• Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.3. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design / MicroarchitectID:58607
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Logic Design Principle EngineerID:58602
20,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The IP Logic Design Principle Engineer will be responsible for architecting microarchitecture design implementation of an IP, spanning across all IP stack such as application layer, transaction layer, link layer, die to die layer, physical layer. Ability to code verilog / system verilog RTL for complex IP, review RTL coding, orchestra IP development phase for projects from beginning to completion. This includes the ability to technically drive the IP team on Design / Validation in completing technical tasks up to IP releases for customers. Candidate must be also capable of solving high speed timing convergence on various processes and collaborate with cross-functional teams to meet project specifications. The role will drive performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Microarchitecture Definitions• Define microarchitecture definition across layers and define a clean inter unit partition requirements.• Drive design team to deliver best-in-class IP design that optimizes for area, latency, power and performance.• Ability to distribute and drive the design team to implement high quality design and meeting time to market requirements.2. IP Design Responsibility• Implement very complicated high-speed design which can converge timing convergence at high frequency.• Capable of orchestrating the team on right directions of timing convergence, CDC, lintra and etc. for tools closure.3. IP Quality Responsibility• Review IP design and validation testplan to make sure IP Design is at top notch quality.4. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNetwork-on-Chip (NoC) Team Engineering DirectorID:58599
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
This role will lead the architecture, design, and development of high-performance interconnect solutions for SoCs, chiplets, and advanced packaging systems. The ideal candidate will have deep expertise in NoC architecture, RTL/micro-architecture design, performance modeling, and verification, combined with strong leadership skills. Experience in both hardware and software development is a strong plus, as it enables system-level optimization, modeling, and seamless HW/SW co-design for next-generation NoC solutions. The NoC Team Director will drive technical strategy, manage execution, mentor a multidisciplinary team, and collaborate with cross-functional partners to deliver state-of-the-art interconnect IP for data-intensive and AI-driven applications. Key Responsibilities1. Leadership & Strategy• Define and execute the company’s NoC technology roadmap, aligned with product and system- level requirements.• Build, mentor, and lead a high-performing team of architects, designers, verification engineers, and performance modelers.• Foster innovation in NoC design, methodology, and automation to achieve best-in-class power, performance, and area (PPA).2. NoC Architecture & Design• Lead the design of scalable, configurable, and high-bandwidth NoC architectures for heterogeneous SoCs and multi-die systems.• Drive micro-architecture, RTL design, and integration of NoC subsystems, including coherency, QoS, and security features.• Oversee performance modeling, traffic analysis, and system-level simulation to ensure NoC meets latency and bandwidth requirements.• Collaborate with physical design teams to optimize NoC topology, floorplanning, and timing closure. 3. Cross-Functional Collaboration• Partner with CPU/GPU/AI accelerator, memory subsystem, and IP teams to define NoC interfaces and integration requirements.• Collaborate with software teams on NoC modeling frameworks, traffic generators, drivers, and firmware for validation and optimization.• Engage with product and system architects to align NoC capabilities with end-market requirements (AI/ML, datacenter, automotive, mobile).4. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
