19 Jobs: Job Vacancies for Circuit Design(Design/Implementation) Positions
IP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan BaruJob Description
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNetwork-on-Chip (NoC) Team Engineering DirectorID:58599
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan BaruJob Description
This role will lead the architecture, design, and development of high-performance interconnect solutions for SoCs, chiplets, and advanced packaging systems. The ideal candidate will have deep expertise in NoC architecture, RTL/micro-architecture design, performance modeling, and verification, combined with strong leadership skills. Experience in both hardware and software development is a strong plus, as it enables system-level optimization, modeling, and seamless HW/SW co-design for next-generation NoC solutions. The NoC Team Director will drive technical strategy, manage execution, mentor a multidisciplinary team, and collaborate with cross-functional partners to deliver state-of-the-art interconnect IP for data-intensive and AI-driven applications. Key Responsibilities1. Leadership & Strategy• Define and execute the company’s NoC technology roadmap, aligned with product and system- level requirements.• Build, mentor, and lead a high-performing team of architects, designers, verification engineers, and performance modelers.• Foster innovation in NoC design, methodology, and automation to achieve best-in-class power, performance, and area (PPA).2. NoC Architecture & Design• Lead the design of scalable, configurable, and high-bandwidth NoC architectures for heterogeneous SoCs and multi-die systems.• Drive micro-architecture, RTL design, and integration of NoC subsystems, including coherency, QoS, and security features.• Oversee performance modeling, traffic analysis, and system-level simulation to ensure NoC meets latency and bandwidth requirements.• Collaborate with physical design teams to optimize NoC topology, floorplanning, and timing closure. 3. Cross-Functional Collaboration• Partner with CPU/GPU/AI accelerator, memory subsystem, and IP teams to define NoC interfaces and integration requirements.• Collaborate with software teams on NoC modeling frameworks, traffic generators, drivers, and firmware for validation and optimization.• Engage with product and system architects to align NoC capabilities with end-market requirements (AI/ML, datacenter, automotive, mobile).4. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Design EngineerID:57868
6,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• To support all analog design activities on company products, design services, physical design implementation as well as internal IP development. Working closely with other engineering and product marketing teams for end product development.• Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug.• Test characterization, measurement and compliance in previous employment.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesAnalog Design Project LeadID:57869
10,000 MYR ~ 12,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• To support all analog design activities on company products, design services, physical design implementation as well as internal IP development. Working closely with other engineering and product marketing teams for end product development.• Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug.• Test characterization, measurement and compliance in previous employment.• To manage the Analog Design team.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesChip Layout Project LeadID:57870
8,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Participate in sub-blocks and module-blocks floor planning and routing from scratch.• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.• Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.• Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesSenior Chip Layout EngineerID:57871
6,000 MYR ~ 8,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Participate in sub-blocks and module-blocks floor planning and routing from scratch.• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.• Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.• Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesSoC Digital DesignID:57872
5,000 MYR ~ 6,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Experience in IP core design such as peripheral interfaces, CPU cores, digital controllers• Architecture review, RTL design, functional verification, post synthesis simulations.• Responsible for SoC system Integration & verification, SoC Architecture and Microarchitecture as well as SoC Peripherals design: GPIO, RTC, UART, 12C, 12S, &SPI• Experience in ARM CPU integration to SoC• Experience in SDRAM Memory Controller integration• Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture• Excellent in Verilog RTL coding and simulation and FPGA prototype and verification• SD/SDIO relative experience is an added advantage.• AMBA Interface relative experience and knowledge in controller design (USB, PCIe, SATA, and Ethernet)
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesSenior SoC Digital DesignID:57873
6,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Experience in IP core design such as peripheral interfaces, CPU cores, digital controllers• Architecture review, RTL design, functional verification, post synthesis simulations.• Responsible for SoC system Integration & verification, SoC Architecture and Microarchitecture as well as SoC Peripherals design: GPIO, RTC, UART, 12C, 12S, &SPI• Experience in ARM CPU integration to SoC• Experience in SDRAM Memory Controller integration• Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture• Excellent in Verilog RTL coding and simulation and FPGA prototype and verification• SD/SDIO relative experience is an added advantage.• AMBA Interface relative experience and knowledge in controller design (USB, PCIe, SATA, and Ethernet)
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesSoC Digital Design Project LeadID:57874
10,000 MYR ~ 12,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Experience in IP core design such as peripheral interfaces, CPU cores, digital controllers.• Architecture review, RTL design, functional verification, post synthesis simulations.• Responsible for SoC system Integration & verification, SoC Architecture and Microarchitecture as well as SoC Peripherals design: GPIO, RTC, UART, 12C, 12S, &SPI.• Experience in ARM CPU integration to SoC.• Experience in SDRAM Memory Controller integration.• Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture.• Excellent in Verilog RTL coding and simulation and FPGA prototype and verification.• SD/SDIO relative experience is an added advantage.• AMBA Interface relative experience and knowledge in controller design (USB, PCIe, SATA, and Ethernet).• Manage and guide the team members.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activities
