31 Jobs: Job Vacancies for Circuit Design(Design/Implementation) Positions

Senior Design Automation Engineer (Analog Mixed-Signal Design)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
Job Description
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Senior Analog Circuit Design Engineer (Highspeed IO Buffer LPDDR6)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
SIPI Engineer (Senior/Staff/Principal)ID:59941
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru
Job Description
Job SummaryResponsible for Signal Integrity and Power Integrity (SI/PI) analysis, simulation, lab validation, and customer support for high-speed digital interfaces across chip, package, and board levels.Key ResponsibilitiesSignal Integrity• Simulation for high-speed interfaces: HBM, DDR, LPDDR, UCIe, MIPI• Crosstalk, reflection, impedance, and eye-diagram analysis• Transmission line modeling and stackup reviewPower Integrity• Power delivery network (PDN) analysis and optimization• Decoupling capacitor selection and validation• PDN impedance measurement and simulation correlationTools & Methods• SI/PI tools: HyperLynx, Ansys SIwave, Cadence Sigrity• Lab equipment: TDR, VNA, high-speed oscilloscope• S-parameter, Y/Z-parameter and multi-port matrix analysis Collaboration• Work with chip, package, PCB design, and layout teams• Support customers on board design reviews and technical queries• Participate in design reviews, failure analysis, and root-cause debugging
Benefit
- Annual Leave 14 days
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Emulation and Prototyping Engineer (Senior/Lead)ID:59881
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
We are seeking a highly skilled and motivated Senior or Lead Emulation and Prototyping Engineer to define and lead emulation strategies for IP, complex SoC and system-level projects. This role requires a strong technical leader who can work independently, while also collaborating closely with system architects and pre-silicon verification teams to drive successful pre-silicon validation, firmware development, and early software enablement using industry-leading emulation/prototyping platforms.Key Responsibilities:• Define and lead the emulation and prototyping strategy for IP & SoC programs to support architectural validation, functional verification, and software bring-up.• Work closely with chip architects to understand IP & system-level design goals and translate them into emulation requirements and constraints.• Collaborate with pre-silicon design verification engineers to integrate emulation/prototyping into the broader verification strategy and identify high-value use cases.• Partition and map RTL designs to commercial emulation/prototyping platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce).• Develop emulation models, transactors, and hybrid environments (e.g., simulation + emulation or virtual platforms).• Lead bring-up and debug activities of the emulation/prototyping environment, ensuring performance, accuracy, and reusability.• Drive the development of automated test environments, infrastructure, and scripts to enable fast deployment and repeatability.• Support firmware and software teams with stable and functional pre-silicon platforms for development and debug.• Maintain comprehensive documentation including emulation and prototyping setup guides, debug workflows, and system usage instructions.• Mentor junior engineers and evangelize emulation best practices across engineering teams.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Advanced Package & Board Team (Senior/Staff/Principal)ID:59718
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
The Advanced Package & Board Team will lead the design, development, and implementation of advanced IC packaging and board-level solutions that enable high-performance, cost-effective, and reliable silicon products. This role requires strong technical leadership across multiple engineering domains — including substrate/interposer design, board design, SI/PI/thermal analysis, and manufacturing interface — while driving cross-functional collaboration with silicon design, system architecture, and OSAT/EMS partners.The successful candidate will define and execute the company’s packaging and board technology roadmap to support next-generation chiplet-based architectures, 2.5D/3D integration, and heterogeneous systems.Key Responsibilities1. Leadership & Strategy• Lead the Advanced Package & Board Design Team, including substrate, interposer, and PCB design engineers.• Define and execute packaging and board technology strategy aligned with company silicon product roadmap.• Establish design and verification methodologies for advanced packaging (e.g., 2.5D, fan-out, chiplet integration).• Drive innovation in thermal management, signal integrity, and power delivery optimization.2. Technical Execution• Oversee design and validation of interposers, substrates, and system boards from concept to production release.• Guide integration of chiplets, HBM, and passive components using state-of-the-art packaging technologies.• Ensure robust SI/PI, mechanical, and thermal analysis for design sign-off.• Collaborate with silicon design teams on bump assignment, die floorplanning, and package co-design.• Manage board-level design for system bring-up, test platforms, and reference designs.3. Supplier & Ecosystem Management• Engage and qualify OSATs, substrate vendors, and PCB manufacturers to ensure quality and yield.• Partner with EDA vendors to establish design automation flow and DRC verification.• Drive technology transfer and pilot runs with manufacturing partners.4. Project & People Management• Plan resources, schedules, and budgets to ensure timely delivery of packaging and board design projects.• Build and mentor a high-performing team with expertise across electrical, mechanical, and materials engineering.• Foster collaboration across silicon, test, reliability, and operations teams.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Senior Standard Cell Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Senior Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Senior Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Senior Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Circuit Design Engineer (Senior/Staff/Principle)ID:59444
6,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
Job Description
Senior/Staff• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.Principle• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery.• Work closely with business development team to understand future projects and resource needed.• First line of clarification and explanation for customer related questions and support.• Work with post silicon team for design intent and required validations.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment