32 Jobs: Job Vacancies for Circuit Design(Design/Implementation) Positions
Senior Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCircuit Design Engineer (Senior/Staff/Principle)ID:59444
6,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Senior/Staff• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.Principle• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery.• Work closely with business development team to understand future projects and resource needed.• First line of clarification and explanation for customer related questions and support.• Work with post silicon team for design intent and required validations.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDesign Verification Engineer (Senior/Staff/Principal)ID:59121
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a highly experienced and technically profound Design Verification Engineer. This role will be responsible for RTL verification, debug, functional coverage and SVA assertion development, UVM testbench development, testplan development and new verification methodology.Key Responsibilities- Develop and maintain UVM-based verification environments for IP designs.- Create detailed test plans based on design specifications, architectural documents, and use-case scenarios.- Implement constrained-random testbenches, scoreboards, and monitors to validate functional behavior.- Perform coverage-driven verification, including:a. Functional coverage (covergroups, coverpoints)b. Code coverage (statement, branch, toggle)c. Assertion coverage (SystemVerilog assertions)- Drive coverage closure by identifying gaps and enhancing test scenarios.- Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis.- Apply Formal Property Verification (FPV) to prove critical design properties and uncover corner-case bugs.- Debug simulation failures and collaborate with RTL designers to resolve issues efficiently.- Document verification results, coverage metrics, and regression summaries for traceability and quality assurance.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCircuit Design Manager / Senior ManagerID:59119
15,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery• Work closely with business development team to understand future projects and resource needed• First line of clarification and explanation for customer related questions and support• Work with post silicon team for design intent and required validations
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan BaruJob Description
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Design EngineerID:57868
6,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• To support all analog design activities on company products, design services, physical design implementation as well as internal IP development. Working closely with other engineering and product marketing teams for end product development.• Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug.• Test characterization, measurement and compliance in previous employment.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesAnalog Design Project LeadID:57869
10,000 MYR ~ 12,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• To support all analog design activities on company products, design services, physical design implementation as well as internal IP development. Working closely with other engineering and product marketing teams for end product development.• Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug.• Test characterization, measurement and compliance in previous employment.• To manage the Analog Design team.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesChip Layout Project LeadID:57870
8,000 MYR ~ 9,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Participate in sub-blocks and module-blocks floor planning and routing from scratch.• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.• Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.• Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesSenior Chip Layout EngineerID:57871
6,000 MYR ~ 8,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Participate in sub-blocks and module-blocks floor planning and routing from scratch.• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.• Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.• Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesSoC Digital DesignID:57872
5,000 MYR ~ 6,000 MYRKota Damansara/Petaling JayaJob Description
【Job Responsibilities】• Experience in IP core design such as peripheral interfaces, CPU cores, digital controllers• Architecture review, RTL design, functional verification, post synthesis simulations.• Responsible for SoC system Integration & verification, SoC Architecture and Microarchitecture as well as SoC Peripherals design: GPIO, RTC, UART, 12C, 12S, &SPI• Experience in ARM CPU integration to SoC• Experience in SDRAM Memory Controller integration• Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture• Excellent in Verilog RTL coding and simulation and FPGA prototype and verification• SD/SDIO relative experience is an added advantage.• AMBA Interface relative experience and knowledge in controller design (USB, PCIe, SATA, and Ethernet)
Benefit
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activities
