Sr Analog Circuit Design Engineer (Clocking)ID:60080

10,000 MYR ~ 22,000 MYRBayan Lepasabout 10 hours ago

Overview

  • Salary

    10,000 MYR ~ 22,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.

    Key Responsibilities
    • Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.
    • Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.
    • Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.
    • Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.
    • Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.
    • Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.
    • Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.
    • Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).
    • Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.
    • Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.

Qualifications

  • Requirement

    • BS or MS in Electrical/Electronics Engineering or related field.
    • Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits.
    • Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects.
    • Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters.
    • Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows.
    • Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment.

    Preferred / Nice-to-Have Experience
    • Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces.
    • Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design.
    • Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics.
    • Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation.
    • Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

  • English Level

    -

  • Other Language

    English

Additional Information

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