Senior Staff IP Logic Design / MicroarchitectID:58607

8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong约15小时 ago

概述

  • 薪资

    8,000 MYR ~ 15,000 MYR

  • 产业类别

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 工作内容

    The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.

    Key Responsibilities:
    1. IP Design Responsibility
    • Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.
    • Ability to produce testplans to cover design requirement

    2. IP Quality Responsibility
    • Ability to execute design validations, FPV, lintra, CDC and etc tools

    3. IP Releases
    • Owning the IP Releases for customer release depending on the assignment

资格

  • 应征条件

    • Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field.
    • Experience in the semiconductor industry for Minimum >5 years’ experience in high speed digital logic design.
    • Strong skills in Logic Design and RTL Coding with Verilog or system Verilog.
    • Experience in high-speed timing convergence in various process node.
    • Deep understanding of Computer Architecture, memory traffic, io controller such as PCIe or UCIe.
    • Excellent problem-solving abilities and attention to detail.
    • Ability to work collaboratively with cross-functional teams for project completion.
    • Ability to execute various IP design tools such as CDC, Lintra, FEV, etc.

  • 英文

    -

  • 其他语言

    English

附加信息

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