9个职位: 招聘信息 研发(工程师(IT/互联网/电信))
Sr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIT Assistant Manager/Senior ExecutiveID:59535
4,600 MYR ~ 8,000 MYRSeputeh, Bangsar工作内容
• Oversees the planning, deployment, and management of all essential IT infrastructure components, including networks, servers and storage.• Working closely with other IT teams, like application development and cybersecurity, to ensure that infrastructure can support new technologies and business initiatives.• Managing the day to day operational and Projects tasks within the IT Infrastructure team.• Managing internal and external communications and being the primary contact of escalation for business issues.• Assisting with the management of relationships with external organisations and suppliers.
福利制度
Salary range: RM4,600 - RM8,000
- Annual Leave
- Medical Leave
- Transport Allowance
- Transport to Client Visit (Claimable)
- Company Parking
- Bonus (Depends company performance - avg 2 months)
- Other benefits will be disclose during interview session.
- Serve 3 years, EPF +4% (lump sum paid on first day of joining to 3rd years)
- Housing Loan Subsidy
- Medical cover Spouse & FamilySr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design / MicroarchitectID:59122
15,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to drive a low power and complex design to completions.2. IP Quality Responsibility• Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.3. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementAI Engineer (Opportunity to work in Japan) ID:58999
3,500 MYR ~ 7,000 MYRMalacca工作内容
The AI Engineer will be responsible for developing, implementing, and maintaining machine learning models and AI solutions to optimize manufacturing processes. This role involves working closely with cross-functional teams to collect data, identify process bottlenecks, and translate operational challenges into data-driven insights that improve productivity, yield, and quality.• Design, develop, and deploy machine learning models to support predictive maintenance, process optimization, defect detection, and yield improvement.• Collect, clean, and preprocess large datasets from production lines, sensors, and quality control systems.• Collaborate with production and equipment engineers to identify use cases for AI implementation.• Develop algorithms for anomaly detection, process control, and root-cause analysis.• Implement data visualization dashboards for real-time process monitoring.• Conduct model performance evaluation and continuous improvement.• Support integration of AI solutions into manufacturing systems (e.g., MES, PLC, SCADA).• Stay updated on AI/ML trends and recommend new tools or technologies for factory digitalization.• Document methodologies and ensure reproducibility of models and results.
福利制度
Salary: ~RM3.5K - RM7K
AL: Starting from 8 days
SL: 14 / 18 / 22 days
<Other benefits>
• Performance bonus - depends on company and individual performance
• Medical coverage
• Personal insuranceIP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNetwork-on-Chip (NoC) Team Engineering DirectorID:58599
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
This role will lead the architecture, design, and development of high-performance interconnect solutions for SoCs, chiplets, and advanced packaging systems. The ideal candidate will have deep expertise in NoC architecture, RTL/micro-architecture design, performance modeling, and verification, combined with strong leadership skills. Experience in both hardware and software development is a strong plus, as it enables system-level optimization, modeling, and seamless HW/SW co-design for next-generation NoC solutions. The NoC Team Director will drive technical strategy, manage execution, mentor a multidisciplinary team, and collaborate with cross-functional partners to deliver state-of-the-art interconnect IP for data-intensive and AI-driven applications. Key Responsibilities1. Leadership & Strategy• Define and execute the company’s NoC technology roadmap, aligned with product and system- level requirements.• Build, mentor, and lead a high-performing team of architects, designers, verification engineers, and performance modelers.• Foster innovation in NoC design, methodology, and automation to achieve best-in-class power, performance, and area (PPA).2. NoC Architecture & Design• Lead the design of scalable, configurable, and high-bandwidth NoC architectures for heterogeneous SoCs and multi-die systems.• Drive micro-architecture, RTL design, and integration of NoC subsystems, including coherency, QoS, and security features.• Oversee performance modeling, traffic analysis, and system-level simulation to ensure NoC meets latency and bandwidth requirements.• Collaborate with physical design teams to optimize NoC topology, floorplanning, and timing closure. 3. Cross-Functional Collaboration• Partner with CPU/GPU/AI accelerator, memory subsystem, and IP teams to define NoC interfaces and integration requirements.• Collaborate with software teams on NoC modeling frameworks, traffic generators, drivers, and firmware for validation and optimization.• Engage with product and system architects to align NoC capabilities with end-market requirements (AI/ML, datacenter, automotive, mobile).4. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
