11个职位: 招聘信息 研发(工程师(IT/互联网/电信))
MLOps DeveloperID:59835
3,500 MYR ~ 7,000 MYRMalacca工作内容
We are seeking an MLOps specialist to architect the infrastructure that allows our AI models to live and breathe on the factory floor. You will be the bridge between model development and industrial production, ensuring our AI systems are scalable, monitored, and resilient enough for 24/7 manufacturing operations• Model Deployment: Lead the transition of models from Jupyter notebooks into production-ready microservices.• Infrastructure Automation: Build and manage the infrastructure required to support LLMs and RAG pipelines at scale.• Observability: Implement logging and alerting systems to detect "model drift" or accuracy drops caused by changes in factory sensor data.• Security Compliance: Ensure all AI tools and internal chatbots meet enterprise security standards and are integrated with company-wide authentication.• Scalability: Optimize AI services to handle high-frequency data from multiple production lines simultaneously.
福利制度
Salary: ~RM3.5K - RM7K
AL: Starting from 8 days
SL: 14 / 18 / 22 days
<Other benefits>
• Performance bonus - depends on company and individual performance
• Medical coverage
• Personal insuranceAOI Engineer (SMT) ID:59838
3,500 MYR ~ 7,000 MYRMalacca工作内容
Automated Optical Inspection (AOI) engineers use specialized cameras, lighting, and image processing algorithms to develop and implement automated systems for detecting defects in manufactured products, particularly printed circuit boards (PCBs), ensuring quality and consistency.Their work involves designing vision systems, training machine learning models to identify flaws, and integrating these systems into production lines to minimize human error and improve manufacturing throughput.• Overcomes manual inspection limitations: AOI systems are faster and more accurate than manual inspection, which is time-consumingand prone to human error.• Ensures precision: Critical for inspecting complex electronics glazed substrate sheets at high speed and high volume• Reduces costs and errors: By catching defects early, AOI reduces rework, minimizes customer returns, and improves overall manufacturing efficiency leading to improved customer delivery• Develops inspection systems: AOI engineers design and build and operate the high-speed camera systems, lighting, and software that power AOI machines.• Programs vision algorithms: Write and refine algorithms that analyze captured images, compare them against a "golden standard" (a perfect reference) and flag any discrepancies.• Implements machine learning: They train machine learning models, including neural networks, to recognize various defects• Integrates systems into manufacturing: integrate these systems into production lines to inspect products at various stages• Enhances quality control: Objective is to provide automated, rapid, and accurate inspection, to ensure higherproduct quality and consistency.• Defect detection: Identifying surface-level issues and trace irregularities.• System calibration and validation: Ensuring the AOI systems are accurate and producing reliable results.• Troubleshooting: Resolving issues with the inspection system or identifying the root causes of recurring defects.• Collaboration: Working with cross-functional teams of engineers and technicians to resolve quality issues.
福利制度
Salary: ~RM3.5K - RM7K
AL: Starting from 8 days
SL: 14 / 18 / 22 days
<Other benefits>
• Performance bonus - depends on company and individual performance
• Medical coverage
• Personal insuranceAI EngineerID:59825
3,500 MYR ~ 7,000 MYRMalacca工作内容
We are looking for a high-potential AI Engineer to help us build "smart" factory systems. • AI Strategy Support: Help contribute to our 3-year roadmap as we move toward autonomous, self-adjusting factory operations.• Data Connections: Help design automated pipelines using SQL Server to connect factory machines and sensors into our central AI system.• Building RAG Systems: Assist in designing and deploying RAG pipelines for our internal AI chatbots to ensure they provide accurate information.• MLOps & Deployment: Work on the full lifecycle of AI models—from development to the factory floor—ensuring they stay accurate and secure.• Collaboration: Work closely with senior engineers and help explain AI results to management and international stakeholders.
福利制度
Salary: ~RM3.5K - RM7K
AL: Starting from 8 days
SL: 14 / 18 / 22 days
<Other benefits>
• Performance bonus - depends on company and individual performance
• Medical coverage
• Personal insuranceData EngineerID:59826
3,500 MYR ~ 7,000 MYRMalacca工作内容
We are looking for a Data Engineer to build the "nervous system" of our factory. You will be responsible for the massive task of connecting physical machines, sensors, and legacy databases into a clean, high-speed data stream that powers our AI models and autonomous decision-making.• Data Ingestion: Lead the design of pipelines that ingest data from SQL Server (e.g., FurnaceTempDB) and factory sensors into a centralized AI-ready format.• Data Quality & Governance: Ensure the data fed into AI models is clean, timestamped accurately, and structured correctly for tasks like "after-firing"dimension prediction.• System Reliability: Maintain 99.9% uptime for data pipelines; if the data stops, the autonomous factory stops.• Storage Strategy: Manage the lifecycle of manufacturing data, balancing the need for "hot" real-time data for AI and "cold" historical data for long-term trend analysis.• Collaboration: Work closely with AI Engineers to provide custom "feature sets" and ensure the RAG system has access to the latest internal documents.
福利制度
Salary: ~RM3.5K - RM7K
AL: Starting from 8 days
SL: 14 / 18 / 22 days
<Other benefits>
• Performance bonus - depends on company and individual performance
• Medical coverage
• Personal insuranceSenior Staff Advanced Package & Board TeamID:59718
15,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior Staff Advanced Package & Board Team will lead the design, development, and implementation of advanced IC packaging and board-level solutions that enable high-performance, cost-effective, and reliable silicon products. This role requires strong technical leadership across multiple engineering domains — including substrate/interposer design, board design, SI/PI/thermal analysis, and manufacturing interface — while driving cross-functional collaboration with silicon design, system architecture, and OSAT/EMS partners.The successful candidate will define and execute the company’s packaging and board technology roadmap to support next-generation chiplet-based architectures, 2.5D/3D integration, and heterogeneous systems.Key Responsibilities1. Leadership & Strategy• Lead the Advanced Package & Board Design Team, including substrate, interposer, and PCB design engineers.• Define and execute packaging and board technology strategy aligned with company silicon product roadmap.• Establish design and verification methodologies for advanced packaging (e.g., 2.5D, fan-out, chiplet integration).• Drive innovation in thermal management, signal integrity, and power delivery optimization.2. Technical Execution• Oversee design and validation of interposers, substrates, and system boards from concept to production release.• Guide integration of chiplets, HBM, and passive components using state-of-the-art packaging technologies.• Ensure robust SI/PI, mechanical, and thermal analysis for design sign-off.• Collaborate with silicon design teams on bump assignment, die floorplanning, and package co-design.• Manage board-level design for system bring-up, test platforms, and reference designs.3. Supplier & Ecosystem Management• Engage and qualify OSATs, substrate vendors, and PCB manufacturers to ensure quality and yield.• Partner with EDA vendors to establish design automation flow and DRC verification.• Drive technology transfer and pilot runs with manufacturing partners.4. Project & People Management• Plan resources, schedules, and budgets to ensure timely delivery of packaging and board design projects.• Build and mentor a high-performing team with expertise across electrical, mechanical, and materials engineering.• Foster collaboration across silicon, test, reliability, and operations teams.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design / MicroarchitectID:59122
15,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to drive a low power and complex design to completions.2. IP Quality Responsibility• Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.3. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
