251 Jobs: Job Vacancies for Selangor Area
【Japanese Speaker】 Customer Service Support ID:59674
5,000 MYR ~ 6,500 MYRKota Damansara/Petaling JayaJob Description
• Handling all inbound calls pertaining to customer general inquiries, complaints, comments, feedback and other raising issue related to the company’s products.• Create & handling all tickets pertaining to customer cases & follows up closely until case resolved.• Working closely with Sales & Level 2 support team members for client contract’s expiration & further technical assistance.• To exceed customer’s expectation in term of customer services & accurate information. Work in a team to achieve the required KPI elements and SLA.• License issue and provision to customer.• Periodic Maintenance Announcement.
Benefit
■Working place: Petaling Jaya, next to Surian MRT
■AL - 12 days
■MC - 14 days
■Medical expense assistance: Company will support up to RM100/monthSales Senior Executive (Japanese Speaker)ID:59672
8,000 MYR ~ 10,000 MYRKepong, Sungai BulohJob Description
・Sales & Business Development: Manage the import and distribution of Japanese food products (snacks, seasonings, etc.) to local retailers and Japanese supermarkets.・Merchandising & Strategy: Collaborate with retailers on floor planning and shelf management to enhance product visibility and consumer appeal.・Promotional Activities: Execute marketing initiatives, including POP displays, promoter management, and organizing "Japan Fair" events.・Market Analysis: Analyze consumer lifestyles and trends to provide tailored marketing solutions and store layouts.・Operations & Follow-up: Oversee the end-to-end sales process from local distribution to delivery (Sourcing is managed by the Japan HQ).・Reporting & Leadership: Manage sales progress for group companies, report to senior management, and lead a local sales team (1–2 subordinates).
Benefit
・Basic Salary: RM 8,000 ~ RM 10,000
・AL: <2Y 12d, 2~3Y 18d, 3~5Y 18d, >5Y 20d
・MC: <2Y 14d, 2~5Y 18d, >5Y 22d
・Medical Benefits
・Medical, Accident and Life Insurance coverage upon confirmation
・Bonus (subject to company performance)
・Company Activities: Team Building, Company TripClient Service ExecutiveID:59669
3,000 MYR ~ 5,000 MYRBandar Sunway/PuchongJob Description
■ JOB OVERVIEWWe are looking for a proactive and logical Client Service Executives to act as a trusted partner to our clients. In this role, your key focus will be approaching new clients, understanding their core business challenges, and leading digital marketing projects to solve them. You will be responsible for the end-to-end process: from conducting client hearings and briefing internal teams, to compiling proposals, presenting solutions, and managing project profitability.While this is fundamentally a client-facing and project management role, logical thinking and data analysis are essential tools you will use daily to identify issues, build persuasive, data-driven proposals, and guide client business to success.■ KEY RESPONSIBILITIES・Client Partnership & Business Development: ・ Approach new clients and conduct thorough hearings to understand their business challenges, target audience, and marketing goals. ・ Build and maintain strong relationships, acting as a collaborative partner dedicated to solving their business issues.・Proposal Creation & Presentation: ・ Translate client challenges into clear, actionable briefs for the creative and production teams ・ Compile comprehensive proposal materials by synthesizing team ideas and utilizing data analysis to back up your strategies. ・ Present ideas, strategic marketing plans, and logical conclusions effectively to clients.・Project & Financial Management: ・ Drive the execution of digital marketing projects (including websites, SNS operations, creative, and online ads) alongside internal teams. ・ Manage project financials, keeping a close eye on revenue, budgets, and profit margins to ensure healthy project P&L. ・ Oversee administrative tasks such as quotations, billing, and schedule management.・Data-Driven Problem Solving: ・ Utilize logical thinking and an evidence-based approach to uncover the root causes of client challenges and formulate effective, realistic solutions.
Benefit
・Salary = RM 4,000 ~ RM 5,500
・Annual leave 12 days/year, increase by years.
・Bonus: once a year
・Incentive: depends on company performance
・Company support parking fee or public transportation fee.
・Private insurance for medical care
・Social Security Contribution
・Education and training
・Overseas Business Travel (Thailand, Vietnam, Singapore)
・Company Trip (depends on company performance)
・Customized education environment by CourseraBusiness Development Executive (KL) (Precious Metals) (Fresh Grads OK)ID:59665
4,000 MYR ~ 6,000 MYRCheras (KL), Cheras (Selangor)Job Description
- Source precious metal scrap (including platinum, gold, and silver) from businesses and individuals in Malaysia and across the region.- Evaluate purchasing decisions to ensure all transactions are profitable.- Prepare proposals and contracts tailored to each customer, based on precious metal valuations and specific requirements.- Monitor market trends and stay informed of changes affecting precious metal pricing and demand.- Assess business performance by identifying strengths, driving operational improvements, uncovering new opportunities, and mitigating potential risks.- Develop and maintain strong customer relationships to grow existing accounts and foster long-term partnerships.- Track and document trade transactions to ensure timely delivery of metals and prompt payment collection.- Collaborate with the marketing team to boost brand visibility and generate qualified leads.- Update the CRM system weekly with supplier details, business leads, and follow-up statuses to maintain accurate records.
Benefit
- Annual Leave
< 2 years : 8 days
2-5 years : 12 days
>5 years : 16 days
- Medical Leave
< 2 years : 14 days
2-5 years : 18 days
>5 years : 22 days
- Medical Claim up to RM 1500 yearly
- Performance Bonus
- Yearly Increment【Japanese Speaker】 Interpreter cum AdminID:59658
4,000 MYR ~ 8,000 MYRKota Damansara/Petaling JayaJob Description
Interpretation and Translation Tasks (Primary Role)-Providing interpretation for the Management Director and Directors.-Interpretation and translation between Japanese and English.-Translate documents and correspondence from Japanese to English and vice versa.￣￣￣￣￣￣￣￣￣￣￣￣￣￣￣-General Affairs & Admin Support-Domestic Travel: Accompanying Directors on business trips within Malaysia (Approx. 3 times/year, up to 3 days and 2 nights).
Benefit
BASIC: RM4,000-RM7,200
Breakdown
-Transport Allowance : RM400
-Gasoline Allowance : RM300
‐Phone Allowance : RM100
-Bonus : Performance change (December/once a year) Average 1 month
‐MC : 14days
-AL : 16days
-Medical InsuranceGenerative AI DesignerID:59650
4,000 MYR ~ 5,500 MYRSeri Petaling, Bandar Sunway/Puchong, Kota Damansara/Petaling JayaJob Description
About the RoleWe are seeking a forward-thinking Generative AI Designer to join our creative team. This role is at the intersection of traditional design excellence and cutting-edge artificial intelligence. You will be responsible for leveraging AI tools to accelerate content creation while maintaining the high aesthetic standards and brand consistency our clients expect.Key Responsibilities1. AI-Assisted Visual Design: Use tools like Nano Banana Pro, Stable Diffusion, Adobe Firefly, and DALL-E 3 to produce high-quality marketing images, social media graphics, product visualizations, and branding elements.2. Prompt Engineering: Research, test, and refine complex AI prompts to achieve specific visual outcomes. Manage parameters, seed controls, and iterative workflows to ensure on-brand results.3. Post-Production & Refinement: Polish and "humanize" AI-generated outputs using traditional tools (Adobe Photoshop, Illustrator, After Effects) to ensure technical accuracy and professional quality.4. Brand Stewardship: Ensure all visual content—whether AI-generated or manually created-adheres strictly to company brand guidelines and maintains a consistent visual identity.5. Innovation & Research: Stay at the forefront of the GenAI landscape. Propose and implement new AI tools and workflows to improve speed-to-market and output quality. 6. Creative Collaboration: Participate in brainstorming sessions with marketing teams to develop campaign concepts and maintain a curated portfolio of AI-assisted work for internal and external showcasing.
Benefit
- Annual Leave: 14 days
- Medical Leave: 14 days
- Parking allowance: RM100
- Medical and dental claims: RM2000/year
- Medical insurance
- Performance bonusSr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr eFUSE Design EngineerID:59655
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an eFUSE Design Engineer to own the end-to-end development of production-grade eFUSE IP on leading-edge process nodes. You will drive eFUSE array architecture, circuit design, full simulation-based verification, collateral and view generation, and quality checks — delivering robust, sign-off-ready eFUSE IP to downstream SoC integration flows. Bitcell-level design knowledge is valued; direct bitcell design experience is a plus but not required. Seniority level to be determined by experience.Key Responsibilities• Design and architect the eFUSE array circuit, including sense amplifier, reference bias, programming current control, address decoder, column multiplexer, and repair logic; ensure correct functional operation across all PVT corners.• Develop and execute comprehensive simulation plans for the eFUSE macro, covering DC/AC characterization, programming/read margin analysis, retention, endurance, and reliability corner simulations (MC, Mismatch, Aging); validate against product specifications and foundry bitcell models.• Generate and validate all required IP deliverable views and collateral: timing models (Liberty .lib), physical abstracts (LEF/GDS), behavioral models (Verilog), datasheets, and application notes; ensure consistency across all views and compliance with delivery checklist.• Define and execute IP quality checks (QC) and quality assurance (QA) regression suites; run DRC/LVS/ERC/PEX sign-off on the eFUSE macro layout; conduct formal and simulation-based functional verification; ensure all sign-off criteria are met prior to IP release.• Collaborate with the foundry and PDK team on eFUSE bitcell characterization data, SPICE models, and process design rules; translate foundry bitcell specifications and reliability requirements into array-level design constraints.• Support Testchip integration of the eFUSE macro, including test circuit design, programming and read test plan development; assist in hardware bring-up, failure analysis, and silicon–to–simulation correlation.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (General Purpose I/O) (GPIO)ID:59654
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.Key Responsibilities• Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).• Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.• Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).• Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.• Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.• Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
