83 Jobs: Job Vacancies for Bayan Lepas Area
NoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan BaruJob Description
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment【Penang】Restaurant Pre-Supervisor / SupervisorID:59304
3,000 MYR ~ 3,500 MYRBayan LepasJob Description
Responsibility• Ensure the team members to all customers are welcomed with clear-greeting and well-guiding to the seat in a courteous and polite manner.• Guide the team with “Added-Value” service to customers. • Keep outlet environment cleanliness and brightness.• Make sure team members are in the proper appearance and posture at all times.• Pay attention to responsibility of outlet sales performance, well-monitoring the stock freshness, manpower management (duty roster planning) and understand general operation cost.• Make sure company regulation in the well keep-running, strict compliance in company standard in hygiene and safety legislation.• Provide leadership guidance, well-communication in coaching and counselling to the duty-in-work team partners.
Benefit
Basic salary : RM3,800-RM4,200
<Additional Allowance>
-Japanese language allowance (Up to RM600)
-Transportation fee is claim based
-EPF, SOCSO, EIS
-Bonus (subject to company performance)
-Meal : Once per day
<AL,MC>
-AL first year 8days
-MC first year 14days
*Subject to changeSenior/Expert System Board Design EngineerID:58749
10,000 MYR ~ 40,000 MYRBayan LepasJob Description
• Lead the end-to-end development of complex multilayer system boards, including architecture definition, schematic design & technical decision-making.• Drive component selection, trade-off analysis & architecture optimization to meet electrical, thermal, and mechanical constraints.• Ensure high-speed signal integrity, power integrity & EMI/EMC compliance through simulation, design & testing.• Lead board bring-up, root cause analysis, and system-level debug using lab instruments (oscilloscopes, logic analyzers, spectrum analyzers, etc.).• Define test strategies and validate hardware against functional, environmental, and reliability requirements.• Prepare and review detailed design documentation: schematics, BOMs, layout constraints, test reports, and manufacturing files.• Collaborate with PCB layout engineers on components placements, routing and PCB stack up.• Skilful on handing rework tool to preforming board rework and modifications to hardware components.• Collaborate with cross-functional teams including SoC, firmware, packaging, mechanical, and manufacturing teams.• Interface with suppliers, PCB fabrication and assembly vendors for prototyping and production.• Provide technical leadership, mentoring, and code/design reviews for junior team members.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementShop Drawing Manager(Penang)ID:59199
7,000 MYR ~ 10,000 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang JayaJob Description
SummaryThe role focuses on preparing and managing shop drawings, coordinating with project stakeholders, and ensuring quality deliverables.Key Responsibilities- Prepare and manage shop drawings for various projects.- Coordinate with Project Managers, consultants, site staff, design teams, and subcontractors regarding shop drawings.- Review and improve details to align with Kajima Standard Details.- Implement Kajima Standard Details in shop drawings.- Maintain and organize project drawing folders and documents in the Common Data Environment (CDE).- Provide shop drawing registers and schedules to Project Managers.- Support site staff and subcontractors in managing shop drawing operations.- Collect feedback from ongoing or completed projects and share insights for improving the quality of deliverables.- Coordinate, guide, and monitor the performance of junior staff involved in shop drawings.
Benefit
- Annual leave: 10 days
- Medical leave: 14 days
- Medical claims: RM1,000/year
- Accommodation
- OT allowance
- Performance appraisal twice yearly.
Mid year - Increment & promotion
Year end - bonus.【JP Speakers】Appraiser(Luxury Goods) in PenangID:59143
4,200 MYR ~ 5,700 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang JayaJob Description
- Verifying the authenticity of designer items by examining their features, such as logos, stitching, and materials, and using specialized tools or techniques.- Evaluating the condition of the items to determine their value. This involves checking for any wear and tear, damages, or repairs that may affect the item's worth.- Setting prices based on the item's authenticity, condition, brand, and market demand. This requires knowledge of current trends and market values for different brands and products.- Keeping up-to-date with trends, new releases, and changes in the fashion industry to ensure accurate assessments and valuations.- Assisting customers with inquiries, providing information about the authenticity and value of items, and offering advice on buying or selling pre-owned goods.- Learn and master appraiser's skill set to assess value of luxury goods across multiple brands, based on authenticity and condition- Answering to phone and whatsapp enquiries of customers looking to sell their pre-loved goods- Build trust and develop long-term relationships with customers, providing excellent service and support to clients- Achieve monthly target for purchasing of goods- No penalty if sell fake
Benefit
- 10 days annual leave (+ 1 day every year)
- Overtime allowance
- Medical insurance (after completion of trial period)
- Bonuses based on company performance and individual performance (once a year)
- Annual salary assessment (linked to performance)Senior Staff IP Logic Design / MicroarchitectID:59122
15,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to drive a low power and complex design to completions.2. IP Quality Responsibility• Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.3. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStaff Design Verification Engineer (DV) / Senior Staff Design Verification Engineer (DV)ID:59121
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a highly experienced and technically profound Staff Design Verification Engineer to take on a technical leadership role in pre-silicon verification for complex, next-generation Application-Specific Integrated Circuits (ASICs). This role is critical in driving verification excellence, setting technical direction, and mentoring local talent.Key Responsibilities• Verification Strategy & Ownership: Define, implement, and lead the overall verification strategy and test plan development (including functional, coverage, and performance) for complex digital ASIC blocks or full chips, ensuring robust quality before tape-out.• Advanced UVM Testbench: Architect, develop, and maintain advanced, reusable UVM-based verification environments using SystemVerilog to enable constrained-random and coverage-driven verification.• C/C++ Programming: Develop C/C++ test cases, firmware test cases for efficient hardware/software co-verification via DPI-C.• Execution and Triage: Hands-on execution of the verification plan, including test case development, regression management, triage, and expert root-cause analysis of functional bugs in RTL and gate-level simulations.• Coverage and Sign-off: Drive and achieve comprehensive functional and code coverage closure goals, utilizing advanced techniques, writing complex assertions (SVA), and ensuring formal verification compliance.• Technical Mentorship: Act as a subject matter expert and mentor to junior and intermediate verification engineers, fostering best practices in coding, methodology, and debug techniques across the team.• Flow Improvement: Evaluate, select, and develop new verification methodologies, tools, and flows (e.g., formal verification, emulation) to enhance the overall team's productivity and quality.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPrincipal Engineer/Principal Architect (Design Verification)ID:59120
20,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced and visionary Principal Engineer/Architect (Design Verification) to lead and drive next-generation design verification strategies, methodologies and execution. The ideal candidate will play a key technical role in shaping DV architecture, methodologies, and execution frameworks to ensure world-class product quality and verification efficiency.Join us if you are a passionate and forward-thinking verification leader who thrives in a fast-paced, innovation-driven semiconductor environment and enjoys mentoring teams, solving complex verification challenges, and influencing design quality and other global engineering teams.Key Responsibilities1. DV Architecture and Methodology Leadership• Define and drive scalable, reusable, and high-efficiency DV architecture and methodology.• Establish verification best practices, including testbench architecture, constrained-random verification, coverage-driven methodologies, and formal verification integration.• Champion automation, regression management, and coverage closure frameworks for continuous efficiency improvement.2. Technical Strategy and Execution• Define verification strategies and verification plans for complex IP design verification (NOC, memory, etc.).• Evaluate and implement state-of-the-art tools, verification techniques, and verification accelerators.• Drive sign-off criteria definition, including functional and code coverage, assertions, and quality metrics.3. Cross-Functional Team Collaboration• Collaborate closely with architecture, design, software teams to ensure robust verification plans and alignment on design intent.• Provide technical guidance to local and global DV teams to standardize and scale best practices.4. Leadership and Mentoring• Mentor and develop technical talent within the DV team, promoting innovation and continuous learning.• Conduct technical reviews, training, and methodology adoption sessions.• Act as a key technical interface with stakeholders and management on DV efficiency and quality metrics.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCircuit Design Manager / Senior ManagerID:59119
15,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery• Work closely with business development team to understand future projects and resource needed• First line of clarification and explanation for customer related questions and support• Work with post silicon team for design intent and required validations
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
