120 Jobs: Job Vacancies for Penang Island Area
[ Penang ] Telemarketer / Inside Sales Executive (12-months Contract - Renewable)ID:58883
2,800 MYR ~ 3,100 MYRBayan LepasJob Description
・Deliver prepared sales talks, reading from scripts that describe products in order to persuade potential customers to know more about our products and schedule appointments for sales representative to meet with prospective customers.・Explain products and answer questions from customers.・Obtain customer information such as name, address and enter information into computers.・Adjust sales scripts to better target the needs and interests of specific individuals.・Learn up product information and knowledge.
Benefit
・Basic Salary = RM 2,500 ~ RM 2,800
・Fixed Car Allowance = RM 300
・Monthly Incentive Scheme up to RM700 (After individually handle project)
・Annual Leave : 12 Days per contract
・Sick Leave: 14 Days
・Half Yearly Bonus
・13th Month Bonus available upon contract renewal
・Claimable Overtime fee
・Parking Subsidy
・Dental / Optical / Health Screening Claimable RM500
・Training providedSales and Marketing Executive (Penang)ID:61296
3,500 MYR ~ 4,400 MYRBayan BaruJob Description
-Promote Company’s Products.-Engage in sales activities by meeting directly with architects and clients to provide product explanations and hands-on demonstrations.-To be a team player for overall work activities.-Liaise with Developer / Architect / Consultant / Main Contractor for product specifications.-Achieve target required.
Benefit
•EPF
•SOCSO
•Bonus : Once a year (average 4month/ depend on company perfomance)
•EIS(Employment Insurance System)
•AL:12days
•MC(Sick Leave):14days
•SIM card （for smart phone) provided
•Competitive basic salary & commission scheme.
•Attractive yearly bonus pay & yearly increment.
•Local & Oversea Company Trip.
•At least one week off during Chinese New Year & Hari Raya celebration without AL or UL deduction.
•Extra one day off on every 31st December.
•Group Personal Accident (GPA) coverage upon confirmation.
•Life insurance coverage for employment 5 years and above.
•Company provides health screening once in 2 years.Technician / Supervisor (Water Treatment System)ID:61295
3,500 MYR ~ 5,500 MYRPeraiJob Description
About the roleWe are seeking a skilled Supervisor - Water Treatment System to join our team at Batu Kawan Hi Tech Park, Penang and Kulim Hi Tech Park. This is a full-time position that requires at least 3 years of relevant experience in the water and waste engineering industry.What you'll be doing- Operate and maintain water treatment systems to ensure optimal performance and compliance with regulatory standards- Conduct routine inspections, testing, and troubleshooting of water treatment equipment and infrastructure- Perform preventative and corrective maintenance on water treatment systems, including pumps, filters, and membranes, EDI, DI columns other components- Collect and analyze water samples to monitor water quality and identify any issues- Maintain detailed records and documentation of all system operations and maintenance activities- Collaborate with the engineering team to implement process improvements and upgrades to the water treatment system- Adhere to all health, safety, and environmental regulations and protocols
Benefit
- Annual Leave 12 days
- Medical Leave 14 days
- Medical Insurance
- OT Claims
- Petrol Claims
- Performance BonusService EngineerID:61294
3,660 MYR ~ 4,660 MYRKulim, PeraiJob Description
- Install, troubleshoot, repair and maintain company equipment.- Perform preventive and corrective maintenance at customer sites.- Provide technical support and resolve customer issues in a timely manner.- Prepare service reports after each site visit.- Conduct equipment testing and calibration where required.- Liaise with customers regarding service schedules and maintenance activities.- Coordinate with the technical teams on customer requirements.- Ensure compliance with company safety procedures and quality standards.- Maintain service tools, spare parts, and documentation.- Perform any other duties assignment by management.
Benefit
- Annual Leave starting from 14 days
- Medical Leave starting from 14 days
- 13 months salary
- Annual Performance Bonus (July)
- Transport Allowance RM100
- Mobile Phone Allowance: RM 60 per month
- Outstation Allowance
- OT Allowance
- On-Call Allowance
- Mileage Claim: RM 0.60 per kilometer
- Toll Fee Claim: As per receipt
- Medical Claim: RM 1,200 per annum
- Dental Claim: RM200 per annum
- Group Personal Accident insurance, hospitalization insuranceAssistant HR OfficerID:61274
3,000 MYR ~ 3,800 MYRPeraiJob Description
- Assist with payroll and salary calculation.- Assist in handling employee discipline, attendance and leave.- Assist with foreign worker matters and related documents.- Arrange and monitor employee training.- Assist with recruitment and new employee matters.- Maintain HR records and documents.- Perform other HR duties as assigned.
Benefit
- Annul Leave 10 days onwards
- Medical Leave 14 days onwards
- Hospitalization leave 60 days
- Insurance Coverage
- Panel Clinic
- Performance Bonus
- Yearly IncrementMemory IP Architect / SoC uArchitectID:61253
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Role OverviewWe are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.Key Responsibilities• NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.• Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.• Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.• Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.• Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.• Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.• Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory IP Architect / SoC uArchitectID:61252
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
We are looking for an experienced Memory IP Architect / uArchitect to lead the architecture and development of next-generation memory solutions for AI, HPC, networking, and custom ASIC applications.This role will drive the definition of memory subsystems, memory controllers, and high-performance SoC memory solutions from concept through silicon.Responsibilities• Define architecture and specifications for Memory IP and SoC subsystems.• Lead memory architecture for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache subsystems.• Drive architecture trade-offs across performance, power, area, and cost.• Develop performance models and conduct architecture exploration.• Define memory hierarchy, and system-level optimization strategies.• Collaborate with RTL, DV, DFT, PD, Packaging, Firmware, and Software teams.• Support customer engagements, technical reviews, and roadmap planning.• Guide implementation through silicon bring-up and performance tuning.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementRTL Design Engineer (Junior/Senior)ID:61251
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Position OverviewWe are seeking RTL Design Engineers at Junior/Intermediate and Senior levels to join our Hardware Engineering team, focusing on ASIC and SoC design.The successful candidates will be responsible for RTL development, functional verification, simulation, debugging and design quality throughout the front-end design flow. Depending on experience and seniority, the role will involve implementing well-defined RTL blocks under guidance or independently owning RTL blocks from specification through verification closure and sign-off.Key ResponsibilitiesA. RTL Design & Development- Develop synthesizable RTL using Verilog and/or SystemVerilog in accordance with design specifications and team coding guidelines.- Implement and maintain RTL blocks for ASIC and SoC designs, ensuring functionality, code quality and design efficiency.- Apply synchronous design principles, including clocking, reset strategies, data valid/ready handshaking and clock domain crossing (CDC) techniques.- Design and maintain functional blocks such as finite state machines (FSMs), FIFOs, arbiters, register files, control logic and data paths.- Work with standard bus protocols, including APB and AHB-Lite, with awareness of AXI4.- Consider area, power and performance (PPA) implications when developing and optimizing RTL.- Collaborate with design, verification, physical design (PD), DFT and other cross-functional teams to resolve design issues and improve implementation quality.Junior / Intermediate Level- Implement well-defined RTL blocks based on detailed microarchitecture specifications under the guidance of senior engineers or technical leads.- Develop foundational knowledge of RTL design methodologies, synthesis implications, CDC concepts and low-power design techniques.- Participate in design reviews, identify potential corner cases and proactively raise technical questions or design concerns.- Improve RTL quality and design efficiency based on code review feedback.Senior Level- Independently own RTL blocks from specification review and design implementation through verification closure and sign-off.- Contribute to microarchitecture definition, design specification documentation and technical design reviews.- Optimize RTL for timing closure, area and power through techniques such as pipelining, retiming and appropriate coding strategies.- Implement and evaluate low-power design techniques, including clock gating, isolation cells and retention flops.- Resolve complex RTL design issues and work with physical design teams to address timing and place-and-route feedback.- Provide technical guidance and informal mentoring to junior engineers.B. Functional Verification & Simulation- Develop and execute directed and self-checking SystemVerilog testbenches to verify RTL functionality.- Run simulations, debug functional failures and analyze waveforms using industry-standard tools.- Write SystemVerilog Assertions (SVA) to capture design intent and verify key interface requirements.- Apply functional coverage concepts to assess verification completeness and identify potential coverage gaps.- Collaborate with design verification engineers to investigate issues and ensure design quality.Junior / Intermediate Level- Develop directed testbenches for assigned RTL blocks and execute simulations using tools such as Synopsys VCS, Questa or Icarus Verilog.- Perform waveform debugging using Verdi, DVE or equivalent tools.- Demonstrate basic understanding of UVM concepts, including agents, sequences and scoreboards.- Add basic functional coverage points and develop familiarity with assertions and verification methodologies.Senior Level- Develop and debug more comprehensive testbenches and contribute to UVM agents, sequences and verification environments.- Interpret coverage reports and drive functional coverage closure in collaboration with verification teams.- Apply assertions, assumptions and cover properties, with exposure to formal verification methodologies.- Investigate complex simulation failures and contribute to root-cause analysis across RTL, verification and integration issues.C. Design Quality, Sign-Off & Integration- Ensure RTL designs comply with applicable design specifications, coding standards and quality requirements.- Review simulation results, lint reports and timing information to identify and resolve potential design issues.- Understand the impact of RTL changes on synthesis, timing, integration and downstream implementation.- Collaborate with verification, DFT and physical design teams throughout the design lifecycle.Junior / Intermediate Level- Develop an understanding of static timing analysis (STA), including setup and hold violations.- Resolve common lint warnings and develop familiarity with CDC analysis and synchronizer insertion.- Understand basic DFT concepts, including scan chains and test modes.- Support design reviews and sign-off activities under senior engineer guidance.Senior Level- Interpret STA reports, timing slack and critical paths, and implement RTL changes to address timing issues.- Resolve common CDC and reset domain crossing (RDC) violations and lint issues.- Apply DFT awareness when designing RTL and supporting scan insertion and test mode requirements.- Work closely with physical design teams to resolve implementation-related issues and support design sign-off.- Take ownership of RTL quality and verification closure for assigned blocks.D. Scripting, Automation & Design Tools- Use scripting languages and automation tools to improve design, simulation and debugging efficiency.- Work with existing simulation flows, tool scripts, file lists and build configurations.- Analyze simulation logs and support the maintenance of design and verification workflows.Junior / Intermediate Level- Write basic Python, Tcl or shell scripts to automate repetitive simulation tasks.- Edit existing Makefiles and Tcl run scripts and parse simulation logs.- Demonstrate proficiency in at least one industry-standard simulation tool.Senior Level- Develop and maintain Python, Tcl or shell scripts for simulation automation, regression execution and log analysis.- Manage file lists, hierarchy extraction and simulation flow configurations.- Troubleshoot tool-flow issues and improve automation efficiency where appropriate.- Utilize synthesis and formal verification tools as required by the project.E. Technical Collaboration & Continuous Improvement- Collaborate with cross-functional engineering teams to support successful ASIC/SoC design implementation.- Participate in design reviews, technical discussions and knowledge-sharing activities.- Maintain clear design documentation and communicate technical issues, progress and blockers effectively.- Continuously improve technical knowledge of RTL design, verification methodologies and EDA tools.Junior / Intermediate Level- Work collaboratively within an established design team, seek clarification when requirements are unclear and incorporate feedback from senior engineers.- Provide timely progress updates and proactively communicate design issues or blockers.Senior Level- Drive technical discussions for assigned RTL blocks and document design decisions and implementation considerations.- Coordinate closely with design verification, DFT, physical design and software teams to resolve technical issues.- Mentor junior engineers and contribute to improving team design practices.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementProduction Manager in Sheet metal department ID:60213
6,000 MYR ~ 8,000 MYRPeraiJob Description
- Production Scheduling & Control: * Develop and execute daily, weekly, and monthly production plans to ensure on-time delivery.- Monitor workflow across sheet metal fabrication processes (laser cutting, bending, welding, assembly, and finishing).Operations & Resource Management:- Optimize the allocation of manpower (50 staff members), machinery, and materials to maximize productivity and minimize waste.- Manage inventory levels of raw materials and work-in-progress (WIP).Quality Assurance & Safety (HSE):- Maintain high-quality standards and implement corrective actions for any defects or non-conformance.- Enforce a safe working environment, ensuring compliance with health and safety regulations and promoting a strong safety culture.Team Leadership & Development:- Lead, mentor, and evaluate a team of 50 factory workers, supervisors, and technicians.- Foster a collaborative environment and manage shift schedules, training, and skill development.Continuous Improvement (Kaizen):- Identify bottlenecks in the production line and implement Lean Manufacturing or Kaizen initiatives to improve efficiency and reduce costs.Reporting & Collaboration:- Report key performance indicators (KPIs) such as OEE (Overall Equipment Effectiveness), delivery rates, and defect rates to upper management.- Collaborate with the Sales, Procurement, and Engineering departments to streamline operations.
Benefit
- EPF, SOCSO provided
- AL:10days(first year), after that additional 2days every year(Maximum 20days)
- MC:14days(first year), after that additional 4days every year(Maximum 22days)
-Transportation allowance:(RM100-200/month depends on range)
-Meal Allowance: (RM100/per month)
-Medical Allowance: RM50/per 1time(unlimited)
-Canteen
-Insurance
-Uniform ＆ Shoes
-Long-service awardField Service Engineer ID:61237
3,000 MYR ~ 4,500 MYRBayan BaruJob Description
• Install, test and commission new equipment at customers’ sites• Carry out equipment assembly, servicing, troubleshooting, repair, upgrade and preventive maintenance• Perform other technical tasks as assigned• Provide and maintain good customer service to customers
Benefit
Salary package: ~RM4,000 - RM4,500
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview session