51 Jobs: Job Vacancies for Bayan Baru Area
【Penang/ Kedah】Sales Representative ID:60191
3,000 MYR ~ 4,000 MYRKulim, Sungai Petani, Tanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya, Butterworth, Bukit Mertajam, Simpang Ampat, Juru, Nibong Tebal, Bukit Minyak, Batu KawanJob Description
We are seeking an aggressive, results-driven Sales Representative to drive Rinnai’s market share in Northern Malaysia. You will be responsible for managing dealer networks, expanding retail penetration, and achieving sales targets for Rinnai’srange of water heaters, gas cookers, indoor heating, and cooling solutions.1. Sales & Business Development・Achieve monthly, quarterly, and annual sales volume and revenue targets for the Northern region.・Collection of payments. Maintain zero overdue.・Identify and onboard new dealers, hardware stores, home appliance retailers, sanitary retailers and service/renovation contractors.・Understand and follows company directions.・Fully comply to company rules and regulations.・Actively participate in ALL company activities.・Ability to understand well on products features and selling points.・Develop and execute territory sales plans to penetrate both urban(Penang/Ipoh) and semi-urban/rural markets.・Plan and coordinate daily sales before meeting up with dealers.・Assist dealers for spare parts purchase and services matters.・Plan dealer visits by town/area.・Constantly update dealers progress on achieving their targets.・Maintain self-discipline and presentable on ALL occasion.・Strictly NO driving after alcohol consumption.・Work and communicate well with all employees.2. Dealer & Channel Management・Build and maintain strong relationships with existing dealers, providing product training and merchandising support.・Ensure Rinnai’s brand visibility through proper display, signage, and promotional materials.・Monitor dealer inventory levels and coordinate restocking with the logistics team.・Conduct mapping exercise and increase distribution channels.・Clearly explain the term and condition for opening dealership.・Participate in All sorts of dealer functions and activities4. Market Intelligence & Reporting・Monitor competitor activities (e.g., Fotile, Rubine, Robam, Joven) on pricing, promotions, and new models.・Submit monthly sales reports, competitor analysis, and customer feedback to the Regional Manager.・Submit monthly PSI report to sales manager.・Submit monthly 3 months forecast, 3 top dealers and by products categories sales.・Track collection of payments and credit terms adherence from dealers. Update account department collection status.5. Promotional Activities・Organize, set promotions price, set-up and participate in roadshows, home fairs, and dealer workshops in the Northern region.・Conduct product demonstrations to end-users at retail points or community events.
Benefit
• Basic salary (RM 2,700 – RM 3,300 depending on experience)
• Sales commission & over-target bonus
• Petrol - MYR 0.6 / per km
• Toll & Parking - claim as per receipt ( during working hour only)
• Medical Allowance - MYR 500 / per year (dental / medical)
• Mobile Phone Allowance - MYR 200 / per month
• Entertainment Claim - MYR 200 / per month
• Travel Allowance - MYR 50 / per day (domestic) & MYR 100 / per day (international) (only for business trip)
• Accommodation - MYR 150 / per night (domestic) & MYR 420 / per day (international) (only for business trip)
• Group insurance Converge - Medical & hospitalisation
•EPF & Socso
• Annual Leave - as per below
Less than 2 years：12 days
Between 2 to 5 Years：17 days
More than 5 years：21 days[ Penang ] Senior Sales Executive (Medical Solutions)ID:60189
4,500 MYR ~ 6,500 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya, Butterworth, Bukit Mertajam, Simpang Ampat, Juru, Nibong Tebal, Bukit Minyak, Batu KawanJob Description
■ JOB SUMMARYWe are looking for a highly driven and results-oriented Sales Executive.You will be responsible for promoting and selling our comprehensive medical equipment and engineering solutions to hospitals, healthcare institutions, and private clinics across Malaysia.You will manage the day-to-day sales pipeline, build strong relationships with medical professionals, and execute the company’s sales strategies to hit revenue targets.You will also be the pioneer in the penetration of Penang market and setting up of Penang branch office.■ KEY RESPONSIBILITIES1. Lead Generation & Client Relationship Management- Identify key decision-makers (hospital administrators, procurement heads, and biomedical engineers) and build commercial relationships.- Actively prospect and expand Hexamine’s business footprint by hunting for new clients and managing existing medical accounts.- Deliver professional presentations to medical clients to explain our value proposition, technology solutions, and services.2. Sales Execution & Tender Documentation- Work aggressively to meet monthly and annual personal sales targets assigned by the company.- Prepare, write, and submit technical proposals, reports, supporting literature, and responses to private and public hospital tender documents.- Actively update the CRM system daily with accurate pipeline progress, client notes, and meeting outcomes.3. Reporting & Strategy Implementation- Execute the sales and marketing strategies laid out for Hexamine's brands to achieve optimal market penetration.- Prepare daily/weekly activity summaries and compile monthly sales forecasts to present to the Head of Sales.- Participate in weekly sales meetings and monitor personal KPI scoring.4. Network Building & Regional TravelSupport the establishment and maintenance of our regional dealership and agent networks across Malaysia.Travel across Northern Region meet regional hospital clients, inspect project sites, or support local dealers.
Benefit
・Basic Salary = RM 4,500 ~ RM 6,500
・Incentive pay out upon project completion
・AL = <5Y 14d, >5Y 16d
・MC = <2Y 14d, 2~5Y 18d, >5Y 22d
・Group Hospitalization
・Panel Doctor (Medical card provided)
・Company Activities: Team Building, Sports Day, CNY Dinner
・Bonus based on company and individual performance[ Penang ] Sales Executive (Medical Solutions)ID:60172
3,500 MYR ~ 4,500 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya, Butterworth, Bukit Mertajam, Simpang Ampat, Juru, Nibong Tebal, Bukit Minyak, Batu KawanJob Description
■ JOB SUMMARYWe are looking for a highly driven and results-oriented Sales Executive.You will be responsible for promoting and selling our comprehensive medical equipment and engineering solutions to hospitals, healthcare institutions, and private clinics across Malaysia.You will manage the day-to-day sales pipeline, build strong relationships with medical professionals, and execute the company’s sales strategies to hit revenue targets.You will also be the pioneer in the penetration of Penang market and setting up of Penang branch office.■ KEY RESPONSIBILITIES1. Lead Generation & Client Relationship Management- Identify key decision-makers (hospital administrators, procurement heads, and biomedical engineers) and build commercial relationships.- Actively prospect and expand Hexamine’s business footprint by hunting for new clients and managing existing medical accounts.- Deliver professional presentations to medical clients to explain our value proposition, technology solutions, and services.2. Sales Execution & Tender Documentation- Work aggressively to meet monthly and annual personal sales targets assigned by the company.- Prepare, write, and submit technical proposals, reports, supporting literature, and responses to private and public hospital tender documents.- Actively update the CRM system daily with accurate pipeline progress, client notes, and meeting outcomes.3. Reporting & Strategy Implementation- Execute the sales and marketing strategies laid out for Hexamine's brands to achieve optimal market penetration.- Prepare daily/weekly activity summaries and compile monthly sales forecasts to present to the Head of Sales.- Participate in weekly sales meetings and monitor personal KPI scoring.4. Network Building & Regional TravelSupport the establishment and maintenance of our regional dealership and agent networks across Malaysia.Travel across Northern Region meet regional hospital clients, inspect project sites, or support local dealers.
Benefit
・Basic Salary = RM 3,500 ~ RM 4,500
・Incentive pay out upon project completion
・AL = <5Y 14d, >5Y 16d
・MC = <2Y 14d, 2~5Y 18d, >5Y 22d
・Group Hospitalization
・Panel Doctor (Medical card provided)
・Company Activities: Team Building, Sports Day, CNY Dinner
・Bonus based on company and individual performanceLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Analog Mixed-Signal Design)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Highspeed IO Buffer LPDDR6)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
