67 Jobs: Job Vacancies for Engineer(IT/Internet/Telecommunications) Positions
IT - Assistant Manager (Melaka)ID:60396
5,000 MYR ~ 6,500 MYRMalaccaJob Description
[Summary]Lead and manage the company's IT infrastructure, security, operations, and technology projects to ensure stable, secure, and efficient business operations. Oversee IT resources, vendors, and team development while driving continuous improvement and compliance.[Job Responsibilities]- Manage and maintain the company's IT infrastructure, including networks, servers, systems, and end-user devices.- Ensure system stability, performance, availability, and timely software and security updates.- Implement and strengthen IT security measures to protect company systems, networks, and data.- Manage data backup, cybersecurity monitoring, threat prevention, and security compliance.- Oversee daily IT operations and provide technical support to ensure business continuity.- Troubleshoot and resolve IT-related issues in a timely manner, including critical incidents and emergencies.- Plan, manage, and execute IT projects and system improvement initiatives.- Coordinate with external vendors and service providers to support business and technology requirements.- Ensure compliance with company policies, SOPs, legal regulations, and IT governance standards.- Manage IT budgets, resource allocation, manpower planning, and cost optimization initiatives.- Lead, coach, and develop IT team members through training, performance management, and career development.- Identify and recommend new technologies and process improvements to enhance operational efficiency and business performance.
Benefit
- Meal Allowance
- Transportation Allowance
- Parking Allowance
- Company laptop and phone provided
- Company Car provided (for Business trips)
- OT: 1.5 times of normal hourly pay
- Salary Increment
- Company Trip
- Bonus
- Replacement Leave (business events are falls on Sat, Sun or PH)
- Annual Leave
- Medical Leave
- EPF, SOCSO
- InsuranceSenior IT Specialist (Local Japanese Speaker)ID:60351
4,500 MYR ~ 6,500 MYRBayan LepasJob Description
Job responsibilities: - Design, develop, test, and maintain in-house software development applications.- Troubleshoot, debug, and upgrade existing software.- Contribute to the continuous improvement of the software development process.- Prepare relevant system and user documentation.
Benefit
- AL: Starting from 10 days
- MC: Starting from 14 days
- Position allowance RM200
- Rental house allowance RM100
- Meal allowance (RM3 per working day)
- Transport allowance based on mileage
- Toll expenses claimable for mainland cdd
- OT claimable
- Company events
- Medical claimable: RM1000, family RM250
- Dental: RM250
- Yearly Increment
- Japanese Language allowance:
N1 RM 500 (Score: above 70%)
N1 RM 400 (Score: below 70%)
N2 RM300
N3 RM200
N4 RM100
N5 RM50Product ManagerID:60341
12,000 MYR ~ 15,000 MYRKota Damansara/Petaling JayaJob Description
Position SummaryThe Product Manager is responsible for driving the growth, adoption, and success of the assigned Zscaler portfolio within the Public Sector and Government-Linked Company (GLC) segments. The role serves as the primary point of contact for Zscaler and is responsible for developing a focused ecosystem of channel partners, creating demand within target accounts and driving sustainable business growth.The successful candidate will combine business development, channel management, customer engagement and vendor management capabilities to achieve revenue, profitability, pipeline and market expansion objectives. The individual must be able to articulate Zscaler's Cloud Security, Zero Trust and SSE/SASE value proposition to partners, end users and key stakeholders within the Public Sector and GLC sectors.Key Responsibilities1. Business Ownership- Own and drive the business performance of the assigned Zscaler portfolio within the Public Sector and GLC segments.- Develop and execute quarterly and annual business plans.- Achieve revenue, gross profit, pipeline and market development targets.- Build and maintain a healthy sales pipeline through partners and end-user engagements.- Conduct regular forecasting and pipeline review sessions.- Identify new business opportunities and develop strategies to increase market share.- Develop and execute account penetration strategies for strategic Public Sector and GLC accounts.2. Vendor Management- Serve as the primary point of contact for Zscaler.- Develop and maintain strong relationships with Zscaler regional and local teams.- Execute joint business plans and quarterly business reviews.- Ensure alignment between vendor objectives and company growth strategies.3. Channel Development- Recruit, enable and develop channel partners focused on Public Sector and GLC opportunities.- Conduct partner business planning and account mapping exercises.- Drive partner certifications, enablement and competency development.- Support partners in identifying, qualifying and closing opportunities.- Establish and maintain a healthy partner ecosystem. - Build strong relationships with key decision-makers within partner organizations.4. Customer Engagement & Solution Positioning- Engage directly with end users, consultants and key stakeholders to create demand and identify opportunities.- Articulate the business and technical value of Zscaler's Cloud Security, Zero Trust and SSE/SASE solutions.- Conduct customer presentations, workshops and executive briefings.- Work closely with pre-sales teams to position solutions and support proof-of-concept activities.- Gather market intelligence and competitive insights to strengthen market positioning.5. Sales Enablement & Collaboration- Work closely with Channel, BD, pre-sales and marketing teams to drive business growth.- Develop sales tools, value propositions and competitive positioning materials.- Support marketing campaigns, seminars, webinars and demand generation activities.- Ensure sales teams are equipped with the knowledge and resources required to position Zscaler effectively.
Benefit
AL
< 2 years : 16 days
2y to 5y : 18 days
>5 years : 21 days
ML
< 2 years : 14 days
2y to 5y : 18 days
>5 years : 22 days
Benefits:
- Office Parking Subsidy
- Contractual Bonus: 1 month
- Optical, dental: RM500 per year
- Health Screening: RM200 per year
- Medical Claims RM 1750 / year for outpatient clinic
- Hospitalization - medical card
- Hospitalization: Cover employee, spouse & child.
- Outpatient clinic: Cover employee, spouse & child.
- Group Term Life InsuranceSenior Software Engineer (C/C++) - PGID:60301
12,000 MYR ~ 15,000 MYRGeorgetownJob Description
- Design, develop, and optimize high-performance trading systems in C++/ C.- Collaborate with traders and engineers to implement new strategies and features.- Work on low-latency networking, real-time data processing, and system reliability.- Contribute to architectural decisions and performance tuning.
Benefit
- AL: starting from 15 days
- MC: starting from 14 days
- EPF, SOCSO, EIS
- Performance bonus
- Paid vacation and daily lunch provided
- Medical, vision and dental coverage
- Health Insurance
- Car park subsidySenior Software Engineer (C/C++) - KLID:60300
12,000 MYR ~ 15,000 MYRDamansara HeightsJob Description
- Design, develop, and optimize high-performance trading systems in C++/ C.- Collaborate with traders and engineers to implement new strategies and features.- Work on low-latency networking, real-time data processing, and system reliability.- Contribute to architectural decisions and performance tuning.
Benefit
- AL: starting from 15 days
- MC: starting from 14 days
- EPF, SOCSO, EIS
- Performance bonus
- Paid vacation and daily lunch provided
- Medical, vision and dental coverage
- Health Insurance
- Car park subsidyDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
