61 Jobs: IT/Telecommunications
Logic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior SAP Consultant（MM）【KL】ID:59727
12,000 MYR ~ 20,000 MYRSingaporeJob Description
【Summary】An SAP MM/EWM-focused ERP implementation consultant responsible for leading end-to-end business transformation and system implementation—from requirements definition and solution design to deployment support—for companies expanding into Southeast Asia.【 Responsibilities 】- ERP (SAP) implementation consulting for companies expanding into Southeast Asia (from planning and solution design through to implementation support)- Driving business transformation and system implementation projects in procurement, inventory, and warehouse management areas in collaboration with the Japanese headquarters- Defining business requirements and conducting Fit/Gap analysis for SAP MM (Materials Management), covering procure-to-pay and inventory management processes.- Supporting SAP EWM (Extended Warehouse Management) implementation and designing integrated solutions with SAP MM.- Supporting the selection of outsourcing partners and collaborating with engineers to design and implement solutions.- Analyzing business challenges in procurement, inventory, and warehouse management processes and proposing process improvements.- Engaging with clients, structuring issues, designing business processes, and providing consulting support in SAP MM/EWM areas.- Depending on the project, may support requirements definition, design, and implementation phases through client-site visits across Malaysia, Singapore, and other Southeast Asian countries.
Benefit
【Singapore Entity】
- Singapore public holidays.
- Annual Leave (AL)
14 days in the first year.
Increases by 1 day for each completed year of service.
- Sick Leave (MC)
14 days in the first year.
Increases by 1 day for each completed year of service.
- Medical & Health Screening Reimbursement
- No medical insurance is provided.
Employees are eligible for reimbursement of actual expenses as follows:
Up to SGD 1,000 per year for outpatient medical expenses (including dependents' outpatient medical expenses).
- Up to SGD 500 per year for annual health screening expenses.
Employees are required to pay the expenses upfront and submit claims for reimbursement.
【Upon Transfer to the Malaysia Entity】
- EPF
- SOCSO
- Annual Leave (AL)
- Medical Leave (MC)
Any additional benefits and allowances will be provided in accordance with the company's policies applicable in Malaysia.Sales and Marketing ExecutiveID:60186
7,000 MYR ~ 10,000 MYRBukit Bintang/KLCCJob Description
- Direct Sales Activities(e-mail/phone calls/business meetings with customers who inquire about the company's services)- Sales promotion support for partners(accompanying business meetings, study sessions, seminars, etc.)- Marketing Support(market research, support for exhibition participation, translation of materials, etc.)- Bridge with Japan headquarters (back office support)-Eventually, support for partners in Singapore and the Philippines- NO sale target and KPI target
Benefit
・Bonus (2months)
・Commuting ＆ Work from Home Allowance 300RM/month
・Business trip allowance
・Global Employee Share Ownership Plan
・14 days of paid leave
*16 days from the 6th year
・14 days of Sick leave
・Private Health Insurance Maximum 1,000RM/year
・Pension
・Workers' compensation
・PC and smartphone provided
・Communication Booster Benefit【JP Speakers】Product MarketingID:60158
6,000 MYR ~ 10,000 MYRBukit Bintang/KLCCJob Description
【Job summary】Product marketer will focus on understanding and marketing the Product (Kintone) to customers.The Candidate drives demand and usage of the product, focusing on processes such as product positioning, sales enablement, product messaging, buyer personas.【Details】● Improve Company product marketing content output● Planning and directing the production of advertisements and content● Targeting and deepening of target audience● Considering what kind of Message or story is effective for Target● Selection of means (media, forms) in line with targets and messages● Management of tags for advertisements● Direction to advertising agencies and production companies● Planning and drafting of LP (web page for advertisement)● Set product marketing budgets and track spend in terms of ROI● Preparation for events such as exhibitions● Check progress with members of the Global Marketing Department in Japan
Benefit
・Bonus (2months)
・Commuting ＆ Work from Home Allowance 300RM/month
・Business trip allowance
・Global Employee Share Ownership Plan
・14 days of paid leave
*16 days from the 6th year
・14 days of Sick leave
・Private Health Insurance Maximum 1,000RM/year
・Pension
・Workers' compensation
・PC and smartphone provided
・Communication Booster BenefitAdmin ExecutiveID:60146
2,500 MYR ~ 3,500 MYRSeputeh, BangsarJob Description
• To manage all executive and confidential matters of the Company.• Responsible for assisting in handling the company’s operation and daily affairs.• Preparation and compilation of report.• To provide general, specialized, confidential and time sensitive operational and administrative support in an accurate and flexible manner.• To provide and maintain a full spectrum of secretarial and administration duties such as arranging meeting schedules, maintaining a proper filing system of documents, etc.• To liaise professionally and strictly confidentially with all levels of management, department, and business associates.• Preparing presentation slides and effectively managing all written communication.• Maintain absolute confidentiality on all given tasks.• Duties will also be extended to projects work on an ad-hoc basis where you will work alongside colleagues from other parts of the business.
Benefit
- Can work from home (Hybrid)
- AL leave
- Birthday leave
- Outpatient claim
- Inpatient claim
- Dental / Optical
- Internet claim
- Parking claim base on receipt
- Gym 50% subsidy - celebrities fitness
- Annual increment / KPI performance review
- Performance BonusMemory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Analog Mixed-Signal Design)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
