67个职位: IT/Telecommunications
Senior UI/UX DesignerID:59486
5,000 MYR ~ 9,000 MYRBangsar工作内容
We are seeking a highly skilled and experienced UI/UX Designer to lead the design of intuitive, engaging, and aesthetically appealing digital experiences across web, mobile, and emerging platforms. As a member of the design team, you will collaborate closely with product managers, engineers, and stakeholders to shape the user journey and define the visual language of our products.Key Responsibilities- Lead end-to-end design process: research, ideation, wireframing, prototyping, UI design, and usability testing.- Translate complex business requirements into intuitive and elegant user-centered solutions.- Create and maintain design systems, UI libraries, and style guides.- Champion UX best practices and advocate for user needs in product planning.- Conduct user research and usability studies to iterate and validate designs.- Collaborate with cross-functional teams to ensure high-quality implementation of designs.
福利制度
Annual Leave:
1-2 years = 12 days
3-4 years = 16 days
5 years and above = 18 days
Bonus:
13th month salary
Allowances:
Transport, Meal, Birthday Allowance
Medical/Dental/Optical claim
Others:
- Sports Activities (Badminton & Basketball)
- Company Outing
- Training and certification sponsored by company (Selected employees).
- Rewards and recognition: Long Service Award / Best Performer Award / Role Model Awards etc
- Project Incentive (upon Company Declaration based on project performance)SAP Consultant - (S4/HANA - FICO/PS)ID:59243
16,000 MYR ~ 25,000 MYRKota Damansara/Petaling Jaya工作内容
We are seeking a highly skilled and motivated SAP S4/HANA FICO/PS CoE Consultant to join our dynamic team. In this role, you will play a pivotal part in maintain template, driving the design, implementation, and continuous improvement of SAP solutions within our organization's finance and project systems landscape. Your expertise in SAP S4/HANA FICO (Financial Accounting and Controlling) and PS (Project Systems) will be essential in optimizing financial processes, enhancing project management capabilities, and ensuring compliance with industry regulations. This role will ensure that the CoE provides strategic direction, best practices, governance, and support for the implementation, optimization, and maintenance of these modules across the organization.Responsibilities:■ Solution Design and Implementation: Collaborate with stakeholders to gather requirements, design and configure SAP S4/HANA FICO and PS modules, and implement solutions that align with business objectives and bestpractices.■ Process Optimization: Analyze existing processes, identify inefficiencies, and propose and implement SAP-based solutions to streamline operations and improve productivity.■ Strategic Alignment: Collaborate with stakeholders to align SAP strategies with corporate objectives and long-term plans. This ensures that SAP implementations support overarching business goals and are adaptable tofuture needs.■ Continuous improvement: Stay abreast of the latest SAP technologies and industry trends, identify opportunities for improvement, and recommend and implement enhancements to optimize system performance and functionality. Stay up-to-date with the latest SAP S/4HANA releases, innovations, and industry trends, and assess their potential impact on the organization.■ Template Governance and Standards: Establish and enforce governance processes, standards, and best practices for SAP FICO/PS modules to to ensure consistency and control across all regional operations. This includes regular reviews and updates in line with evolving business and regulatory requirements. Develop and maintain documentation standards and their updates for configurations, processes.■ Compliance and Risk Management: Ensure that SAP solutions comply with relevant financial regulations and internal controls, minimizing financial risks.
福利制度
・Salary = RM 16,000 - RM 25,000 (Gross)
・AL = <2Y 15d, 2~5Y 19d, >5Y 22d
・MC = <2Y 14d, 2~5 18d, >5Y 22d
・Mobile Allowance = RM 100
・Transport Allowance = RM 450
・All business travel claimable
・Outstation Allowance (amount based on location)
・Overseas Allowance (amount based on location
・Mileage = RM 0.70 / km (within Klang Valley travel)
・Medical Claim = RM 10,000 / year (including specialist)
・Flexi Plan up to RM 1,000 (Including dental, optical, and productivity gadgets)
・Insurance: Tokio Marine (PA, Hospitalization)
・Company Activities: Annual Dinner (by division), Sport Carnival (for all Panasonic group companies)
・Mobile Phone Allowance (Upon confirmation)
・Dental, Vision, Outpatient, Group Hospitalization, etc.Execution Specialist - Algorithmic ExecutionID:59481
4,500 MYR ~ 5,500 MYRDamansara Heights工作内容
Key Responsibilities- Algorithm Deployment & Monitoring: Oversee live execution algorithms, applying system-defined parameter adjustments based on real-time performance metrics.- Market Awareness: Maintain continuous awareness of market conditions, indices, asset price movements, and relevant announcements.- Performance Optimization: Monitor execution metrics (e.g., latency, fill quality), identify issues, and apply predefined adjustments within documented procedures.- Post-Execution Analysis: Analyze execution outcomes using Python (Pandas, NumPy) and deliver actionable insights.- Technical Coordination: Collaborate with our Penang-based technology team to communicate operational issues and validate system enhancements.- Risk Management & Controls: Operate within strict risk frameworks, documenting and escalating incidents transparently. All algorithm adjustments follow predefined rules—no discretionary authority is granted.- Execution Data Ownership: Ensure the accuracy and availability of execution data for ongoing analysis and strategy refinement.
福利制度
- Fixed Transport Allowance
- Performance bonus
- Evaluation twice a year
- Health Insurance
- Lunch subsidy by company
- EPF, SOCSO and EIS
- Medical, vision and dental coverage
- Car park subsidyStrategy ManagerID:59478
10,000 MYR ~ 15,000 MYRDamansara Heights工作内容
SummaryThe role will involve analyzing and providing solutions to businesses problems, as well involvement in overseeing development of the proposed solutions and finally completion of the projects. There will also be participation in executing plans to managing change impacts to our customers’ organization.Key Responsibilities:Business1.Market Research - gathering market information to be used for data analysis and provide analysis & conclusion for market research2.Gather business information to be used for business process improvement analysis and provide assessment, recommendation and conclusion on the analysis.3.Recommend solutions based on analysis, logical thinking and problem-solving skillsProjects1.Assist in formulating and execute project governance, monitors and controls.2.Assist in formulating project tracking and execute progress monitoring.3.Will be project knowledge source of reference for the project team.4.Coordinating and streamlining all activities within a project.Change1.Execute plans in managing people and organization changes.2.Involved in planning and executing communication, trainings, and stakeholder management.3.Lead the support and alignment to project activities.
福利制度
・AL: 16d
・MC: 22d
・Handphone Allowance = RM 50
・Medical Claim: Single RM 1,800, Married RM 2,250
・Hospitalization Leave = 60d
・Hospitalization Claim: up to RM 60k
・Season Parking: Paid on monthly reimbursement basis
・Fitness Allowance: Claimable up to RM 360 per quarter or RM 120 monthly
・Dental, Optical claim
・Regular Company Events: Sports Tournament, Outdoor Activities
・Bonus based on company and individual performance
・Access to fitness, dental, and optical benefits.
・Regular company events, including sports tournaments and community activities.Sr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Staff/Principal Engineer, Circuit DesignID:59444
6,500 MYR ~ 8,500 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru工作内容
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
