Logic Design Verification EngineerID:60088

8,000 MYR ~ 16,000 MYRBayan Lepasabout 5 hours ago

Overview

  • Salary

    8,000 MYR ~ 16,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking to hire Logic Verification Engineer. Familiarity with LPDDR and HBM memory interface IP will be a plus. Seniority level to be determined by experience.

    Key Responsibilities
    • Develop and maintain UVM-based verification environments for various IPs, including constrained-random testbenches, protocol-aware monitors, scoreboards, and checkers.
    • Author detailed verification plans based on specifications, architectural documents, and use-case scenarios; own coverage closure end-to-end.
    • Drive coverage-driven verification (CDV): functional coverage (covergroups/coverpoints), code coverage (statement, branch, toggle), and SystemVerilog assertions (SVA); identify gaps and close with targeted test scenarios.
    • Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis; apply Formal Property Verification (FPV) to prove critical design properties.
    • Debug simulation failures in collaboration with RTL designers; document results, coverage metrics, and regression summaries for traceability and sign-off.

Qualifications

  • Requirement

    • Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or related field.
    • Solid hands-on experience with UVM testbench development and SystemVerilog; ability to write maintainable, well-structured verification components independently.
    • Experience with coverage-driven verification and SVA assertions; demonstrated ability to close coverage on a non-trivial IP block.
    • Proficiency in scripting (Python, Perl, or shell) for regression automation and verification flow support.
    • Strong analytical and debugging skills; ability to collaborate across RTL design and architecture teams to drive issues to closure and communicate results clearly.

    Preferred / Nice-to-Have
    • Working knowledge of high-speed memory interface protocols LPDDR or HBM, at the architectural or verification level; familiarity with JEDEC specifications and DFI interface.
    • Experience developing Bus Functional Models (BFMs) for memory interface protocols.
    • Exposure to Formal Property Verification (FPV) tools (JasperGold, VC Formal) and methodology.
    • Familiarity with emulation or FPGA prototyping environments and post-silicon bring-up support.
    • Prior experience with related high-speed IP such as PCIe, UCIe, Ethernet, or AXI interconnect verification.

  • English Level

    -

  • Other Language

    English

Additional Information

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