Overview

• Salary

  8,000 MYR ~ 15,000 MYR

• Industry

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• Job Description

  We are seeking an experienced and strategic Senior or Staff DFT Design Engineer to join our team and in support the company’s ASIC design and IP development initiatives in the area of Design for Testability (DFT) design and verification. The candidate will play a key role in leading the planning and execution of various DFT features implementation and verification.
  
  Key Responsibilities:
  • DFT microarchitecture planning, DFT rtl generation/integration and verification of various DFT feature.
  • Memory BIST design implementation and verification for IP and ASIC projects.
  o Mbist logic insertion, integration and verification.
  o Mbist collateral generations including mbist pattern and timing constraint.
  • Scan design implementation and verification for IP and custom ASIC.
  o Scan controller generation (clock/reset control, test compression) implementation and scan chain stitching
  o ATPG pattern generations and GLS simulation to verify the scan design.
  o Scan collaterals generation including scan constraint, scan timing closure, ATPG pattern debug etc.
  • JTAG/Boundary Scan design implementation and verification
  o Tap controller design and verification
  o Boundary scan chain implementation at IP and soc level, bscan verification and bsdl generation.
  • Post silicon debug and test pattern bring up supports to enable silicon power on activities and high-volume manufacturing testing.