Overview

• Salary

  10,000 MYR ~ 20,000 MYR

• Industry

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• Job Description

  Role Description
  This is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.
  
  The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.
  
  Key Responsibilities
  1. Block Ownership and RTL Design Implementation
  • Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.
  • Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.
  • Ensure compliance with architecture specifications and coding guidelines.
  • Understand PHY–Firmware interaction for training, calibration, and initialization sequences.
  • Develop local testbenches to functionally verify assigned PHY sub-blocks.
  • Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.
  
  2. Behavioral Modeling and Verification Support
  • Develop and maintain behavioral models for PHY sub-blocks.
  • Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.
  • Provide model updates to align with design and architectural changes.
  
  3. Constraint and Power Intent Definition
  • Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.
  • Validate constraint correctness and ensure smooth handoff to STA and physical design teams.
  
  4. Static Verification (Lint / CDC / RDC)
  • Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.
  • Review and debug violations, provide waivers with technical justification.
  • Support and guide the design team in interpreting and resolving RDC-related issues.
  
  5. Code Coverage and Waivers
  • Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.
  • Participate in coverage reviews and track closure progress toward sign-off.