75个职位: 峇六拜 Bayan Lepas最新招聘信息
Advanced Package & Board Team (Senior/Staff/Principal)ID:59718
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Advanced Package & Board Team will lead the design, development, and implementation of advanced IC packaging and board-level solutions that enable high-performance, cost-effective, and reliable silicon products. This role requires strong technical leadership across multiple engineering domains — including substrate/interposer design, board design, SI/PI/thermal analysis, and manufacturing interface — while driving cross-functional collaboration with silicon design, system architecture, and OSAT/EMS partners.The successful candidate will define and execute the company’s packaging and board technology roadmap to support next-generation chiplet-based architectures, 2.5D/3D integration, and heterogeneous systems.Key Responsibilities1. Leadership & Strategy• Lead the Advanced Package & Board Design Team, including substrate, interposer, and PCB design engineers.• Define and execute packaging and board technology strategy aligned with company silicon product roadmap.• Establish design and verification methodologies for advanced packaging (e.g., 2.5D, fan-out, chiplet integration).• Drive innovation in thermal management, signal integrity, and power delivery optimization.2. Technical Execution• Oversee design and validation of interposers, substrates, and system boards from concept to production release.• Guide integration of chiplets, HBM, and passive components using state-of-the-art packaging technologies.• Ensure robust SI/PI, mechanical, and thermal analysis for design sign-off.• Collaborate with silicon design teams on bump assignment, die floorplanning, and package co-design.• Manage board-level design for system bring-up, test platforms, and reference designs.3. Supplier & Ecosystem Management• Engage and qualify OSATs, substrate vendors, and PCB manufacturers to ensure quality and yield.• Partner with EDA vendors to establish design automation flow and DRC verification.• Drive technology transfer and pilot runs with manufacturing partners.4. Project & People Management• Plan resources, schedules, and budgets to ensure timely delivery of packaging and board design projects.• Build and mentor a high-performing team with expertise across electrical, mechanical, and materials engineering.• Foster collaboration across silicon, test, reliability, and operations teams.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Standard Cell Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment[ Penang ] Business Development Senior Executive (Specialty Metal)ID:59579
8,000 MYR ~ 10,000 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya, Butterworth, Bukit Mertajam, Simpang Ampat, Juru, Nibong Tebal, Bukit Minyak, Batu Kawan工作内容
< About the Role >We are looking for an experienced Business Development Assistant Manager to lead sales initiatives in Malaysia.The successful candidate will have a strong network in the specialty metals and precision machining industries, and will be tasked with identifying new business opportunities, maintaining client relationships, and driving sales growth.< Key Responsibilities >• Identify and pursue new business opportunities across Malaysia• Maintain strong relationships with key clients and decision-makers• Achieve monthly and annual sales targets• Conduct market research and competitive analysis• Develop proposals, quotations, and pricing strategies• Negotiate and close deals, ensuring timely payment collection• Prepare sales reports and track performance metrics• Collaborate with the Sales Director and Singapore HQ• Travel extensively within Malaysia (and occasionally to Singapore)• Report regularly via digital tools (email, Google Sheets, CRM)
福利制度
・Total Salary = RM 8,000 ~ RM 10,000
・Transportation expenses within Malaysia and Mobile Phone expenses will be a fixed monthly allowance.
・Traveling out of Malaysia will be on a reimbursement basis e.g. to Singapore.
・EPF and Socso will be provided.
・Commission Scheme: Performance-based, up to 20% of base salary
・Other benefits packages are open to be discussed during interviewProduct Specialist (Penang) (PN & EN)ID:59552
3,500 MYR ~ 5,000 MYRTanjung Tokong, Tanjung Bungah, Gelugur, Georgetown, Jelutong, Air Itam, Bayan Lepas, Bayan Baru, Batu Maung, Bukit Jambul, Perai, Sebarang Jaya, Butterworth, Bukit Mertajam, Simpang Ampat, Juru, Nibong Tebal, Bukit Minyak, Batu Kawan, Kota Damansara/Petaling Jaya工作内容
• Responsible for achievement of the assigned territory’s Sales Budget • Maintain, cultivate and expand existing customers in line with Company’s growth strategies • Organize and conduct CME (Continuing Medical Education) activities to promote the specific product assigned • Maintain an updated comprehensive and classified list of physicians, hospitals and paramedical contacts • Regular reporting of market intelligence
福利制度
【Benefits】
- Annual Leave
- Medical Leave
- EPF Contribution
- SOCSO
- Entertainment Claims
- Company Team Building
- Insurance Coverage
- Medical Claims
- Optical & Dental Claims
- Performance Bonus
- Incentive Upon Hitting KPI
- Flexible Work Arrangement
- Fully Work From Home (WFH)
- Vehicle/ Transport Allowance[ Penang ] Sales & Application EngineerID:59456
4,000 MYR ~ 6,000 MYRBayan Lepas工作内容
・Development & implementation of the factory automation solution strategies using Industry 4.0 technologies in line with the company’s business vision & goals ・Execution of the sales workflow and to discover the opportunities and markets for IIoT and Industry 4.0 solutions・Coordination of proposal workflow ・Execution of the project workflow (Planning, Scope, Budget, Quality, Documentation)・Present and offer solutions to customers that include: Production Performance & Andon System / Energy Monitoring System / Condition Monitoring System / Track & Trace System / Process Monitoring & Control / Wireless Data Acquisition System. ・Automation software used to offer solutions to customers include PLC / IPC / SCADA / SQL ・Calculate engineering services based on or customer requirements (FDS/TDS)・Coordinate small/midrange projects from specification > engineering > testing > commissioning > support・Train & support application services to customers
福利制度
・Basic Salary = RM 4,000 ~ RM 6,000
・AL: <2Y 12D, <5Y 16D, <10Y 20D, >11Y 22D
・MC: <2Y 14D, 2~5Y 18D, >5Y 22D
・Car Allowance = RM500
・Petrol Fleet Card @ RM420
・Sales Incentive
・Year End Bonus (based on company performance) ** Average 1 monthCircuit Design Engineer (Senior/Staff/Principal)ID:59444
8,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment【Penang】Restaurant Pre-Supervisor / SupervisorID:59304
3,000 MYR ~ 3,500 MYRBayan Lepas工作内容
Responsibility• Ensure the team members to all customers are welcomed with clear-greeting and well-guiding to the seat in a courteous and polite manner.• Guide the team with “Added-Value” service to customers. • Keep outlet environment cleanliness and brightness.• Make sure team members are in the proper appearance and posture at all times.• Pay attention to responsibility of outlet sales performance, well-monitoring the stock freshness, manpower management (duty roster planning) and understand general operation cost.• Make sure company regulation in the well keep-running, strict compliance in company standard in hygiene and safety legislation.• Provide leadership guidance, well-communication in coaching and counselling to the duty-in-work team partners.
福利制度
Basic salary : RM3,800-RM4,200
<Additional Allowance>
-Japanese language allowance (Up to RM600)
-Transportation fee is claim based
-EPF, SOCSO, EIS
-Bonus (subject to company performance)
-Meal : Once per day
<AL,MC>
-AL first year 8days
-MC first year 14days
*Subject to change
