63个职位: Software/Information Processing
Senior Procurement Engineer (PG)ID:60273
5,000 MYR ~ 8,000 MYRSimpang Ampat, Batu Kawan工作内容
The Senior Procurement Engineer will be responsible for the global category management of raw materials and supply chain activities within R&D locally, with a focus on technical commodities such as metals and plastics. This role requires strong technical knowledge, supplier management expertise, and the ability to drive cost, quality, and delivery improvements in alignment with project and business objectives.Key Responsibilities:- Identify and implement initiatives to improve supplier base and supply assurance, including sourcing new/current approved suppliers, enhancing quality, lead time, delivery, and cost efficiency.- Lead the RFQ process and manage direct commodities in standard and fabrication parts, ensuring materials and services meet approved specifications and departmental goals.- Establish and maintain strong relationships with suppliers, promoting continuous technology and process improvements through regular communication and evaluation.- Negotiate and enforce best practices across 5Rs (Right Quality, Right Quantity, Right Time, Right Place, Right Cost) in RFQs and contract terms to maximize value for money.- Act as a business partner with relevant functions (BU, R&D, and Projects) throughout the procurement process, ensuring timely and efficient delivery of materials and services.- Coordinate and resolve procurement and supply chain issues to meet project deliverables with high quality standards.- Ensure compliance with company supply chain and procurement processes, as well as perform other tasks as assigned by supervisor or leadership.
福利制度
- Phone allowance
- OT allowance
- Optical / Dental = RM300
- Medical = RM500
- Annual Leave
- Compassionate Leave
- Marriage Leave
- Travel AllowanceMechanical Design Engineer / Mechanical Engineer (PG)ID:58969
10,000 MYR ~ 12,000 MYRBatu Kawan工作内容
Core Duties:1. Responsible for project design and planning.2. Drafting technical drawings and preparing related documentation.3. Managing drawings and design documents.4. Troubleshooting design issues during product trial production.Job Responsibilities1. Project design and planning.2. 3D design for projects.3. Preparation of 2D drawings, BOMs, operation manuals, and maintenance manuals. 4. Drafting other technical documentation.5. Organizing, compiling, and archiving project materials.
福利制度
- Phone allowance
- OT allowance
- Optical / Dental = RM300
- Medical = RM500
- Annual Leave
- Compassionate Leave
- Marriage Leave
- Travel AllowanceJunior ProgrammerID:60264
4,000 MYR ~ 6,000 MYRKL Sentral工作内容
Main role : handles the projects passed by Japan HQ. Current main project on going is Related to API programing used for client's software developing solutions.Currently in charge is more maintenance and new integration projects, but eventually once the team is expanding number of projects to handle would be increasing. 1. Coding, testing, user training, documentation, post-implementation support, debugging, and bug fixing.2. Actively participate in the development and execution of QA test plans for System Integration Tests (SITs) and User Acceptance Tests (UATs).3. Engage in coding and hands-on development activities. To support continuous improvement activities, which including troubleshoot, debug, and upgrade existing software and applications. To involve actively in peer reviewing each other code and provide high quality output4. Responsible for estimating the time needed to complete each task, contributing to the achievement of project goals
福利制度
- Transportation for commuting : claimable
- Office Parking is claimable
- AL : 12 days for the 1st year (after 2 years service increases 2 days)
- MC : 14 days (after 2 years service increases 2 days)
- Medical claimable RM1,000/year includes specialist and medical check up
- Professional Training & Development Opportunities
- Quarterly Company Activity or Event in Kuala LumpurSenior/Staff Design for Testability (DFT) EngineerID:60263
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced and strategic Senior or Staff DFT Design Engineer to join our team and in support the company’s ASIC design and IP development initiatives in the area of Design for Testability (DFT) design and verification. The candidate will play a key role in leading the planning and execution of various DFT features implementation and verification.Key Responsibilities:• DFT microarchitecture planning, DFT rtl generation/integration and verification of various DFT feature.• Memory BIST design implementation and verification for IP and ASIC projects.o Mbist logic insertion, integration and verification.o Mbist collateral generations including mbist pattern and timing constraint.• Scan design implementation and verification for IP and custom ASIC.o Scan controller generation (clock/reset control, test compression) implementation and scan chain stitchingo ATPG pattern generations and GLS simulation to verify the scan design.o Scan collaterals generation including scan constraint, scan timing closure, ATPG pattern debug etc.• JTAG/Boundary Scan design implementation and verificationo Tap controller design and verificationo Boundary scan chain implementation at IP and soc level, bscan verification and bsdl generation.• Post silicon debug and test pattern bring up supports to enable silicon power on activities and high-volume manufacturing testing.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 18,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design EngineerID:60086
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Logic Design Engineer to implement RTL design. Familiarity with LPDDR and HBM memory interface IP will be a plus. The engineer will own block-level microarchitecture, RTL coding, and design sign-off from specification through customer delivery. Seniority level to be determined by experience.Key Responsibilities• Define and implement block-level and layer-level RTL for various IPs, meeting high-frequency timing requirements at advanced process nodes.• Drive microarchitecture definition for assigned blocks in collaboration with senior architects; document design decisions and trade-offs clearly for cross-functional review.• Achieve timing closure at high frequencies; work with physical design and STA teams to resolve setup/hold violations, manage clock domain crossings (CDC), and support floorplan iterations.• Execute design quality checks: CDC analysis, lint (Lintra), formal equivalence verification (FEV), and low-power (UPF) flows; resolve violations to achieve clean convergence.• Produce and review test plans for block-level functional verification, including black-box and white-box simulation, FPV, and emulation; collaborate with DV engineers to resolve design bugs.• Own IP release deliverables for customer handoff: RTL packages, netlists, and accompanying documentation; ensure release quality and compliance with customer specification.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Mechanical Design EngineerID:60144
5,200 MYR ~ 6,700 MYRBayan Lepas工作内容
- Design and develop mechanical systems for automated vision inspection systems for wide range of industrial applications.- Review equipment design for compliance with engineering principles, company standards, product requirements and related specifications.- Collaborate with vision software team on system integration jobs from design stage until system delivery.- Manage system integrators, equipment suppliers, contractors and other external vendors to meet project objectives.- Perform onsite system setup, troubleshooting and provide technical assistance to customers when necessary.
福利制度
- Annual Leave: 14 days
- Medical Leave: 14 days
- Transport Allowance
- Phone Allownace
- Medical Claims
- Insurance Coverage
- Performance Bonus
- Yearly Increment
- Company TripMechanical Design Team LeadID:60143
6,300 MYR ~ 8,300 MYRBayan Lepas工作内容
- Lead and execute full mechanical design cycle from concept to FAT/SAT of precision automation modules. - Deliver accurate 3D models, GD&T drawings, tolerance stacks, BOMs, simulations and costed proposals that meet stability, repeatability, precision and safety targets. - Sync mechanical interfaces with electrical, software, manufacturing, QA, purchasing and field teams; clarify build issues, drive root-cause fixes and update standards. - Provide rapid feasibility sketches, cycle-time studies, risk lists and cost estimates for RFQs; act as the primary mechanical authority in customer meetings, FAT/SAT and site installs. - Diagnose and correct on-site issues, document lessons-learned and embed them in updated templates and design guides. - Maintain revision control, file naming, drafting standards and a library of reusable components/modules to shorten future design cycles. - Allocate tasks, track schedules, mentor juniors in DFM/DFA and tolerance logic, run weekly reviews, conduct training and performance appraisals to build a high-performance mechanical team.
福利制度
- Annual Leave: 14 days
- Medical Leave: 14 days
- Transport Allowance
- Phone Allownace
- Medical Claims
- Insurance Coverage
- Performance Bonus
- Yearly Increment
- Company TripLogic Design Verification EngineerID:60088
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking to hire Logic Verification Engineer. Familiarity with LPDDR and HBM memory interface IP will be a plus. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain UVM-based verification environments for various IPs, including constrained-random testbenches, protocol-aware monitors, scoreboards, and checkers.• Author detailed verification plans based on specifications, architectural documents, and use-case scenarios; own coverage closure end-to-end.• Drive coverage-driven verification (CDV): functional coverage (covergroups/coverpoints), code coverage (statement, branch, toggle), and SystemVerilog assertions (SVA); identify gaps and close with targeted test scenarios.• Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis; apply Formal Property Verification (FPV) to prove critical design properties.• Debug simulation failures in collaboration with RTL designers; document results, coverage metrics, and regression summaries for traceability and sign-off.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDFT Logic Design EngineerID:60087
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a DFT Logic Design Engineer to implement testability infrastructure across our digital IP portfolio. You will define DFT strategy, integrate scan and BIST structures at the RTL level, and drive fault coverage from early design through silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Define and own the DFT architecture for digital and mixed-signal blocks: scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, and MBIST/LBIST planning; document and maintain the DFT specification throughout the design cycle.• Develop and integrate DFT RTL (SystemVerilog/Verilog): scan wrappers, BIST controllers, test access ports, and clock/reset control logic; ensure DFT structures are synthesis-clean, timing-closed, and do not degrade functional performance or power.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets; achieve and sign off on target fault coverage metrics agreed with the test engineering team.• Collaborate with RTL designers on DFT-aware coding guidelines; perform DFT rule checking, CDC analysis, and Lint to identify and resolve testability violations early in the design cycle before netlist handoff.• Support physical design handoff: provide scan chain ordering recommendations, validate DFT netlist post-layout (LEC, STA), and resolve DFT-related ECOs during timing closure and tapeout.• Support post-silicon validation and ATE bring-up: work with test engineers to load and debug ATPG patterns on ATE platforms, analyze yield data, and triage failing patterns back to root-cause RTL or physical design issues.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
