39个职位: Software/Information Processing
Sr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Staff/Principal Engineer, Circuit DesignID:59444
6,500 MYR ~ 8,500 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru工作内容
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementProgram Executive (Cybersecurity Awareness Program) ID:59367
3,800 MYR ~ 4,000 MYRKota Damansara/Petaling Jaya工作内容
1. Client Engagement & Program Ownership• Serve as the main point of contact for assigned clients throughout their CSAT Managed Services engagement.• Understand client needs, business environment, and risk areas to tailor program strategy accordingly.• Build strong relationships with key stakeholders from IT, HR, Compliance, and Leadership teams.• Conduct monthly or quarterly review sessions to present results, insights, and improvement recommendations.2. Program Planning & Execution• Develop annual CSAT program plans, including training roadmaps, phishing simulation calendars, and awareness reinforcement activities.• Configure, maintain, and manage campaigns within the CSAT platform (user onboarding, segmentation, training assignments, notifications).• Ensure timely execution of monthly simulation campaigns and training rollouts.• Continuously monitor program health, identifying potential gaps or areas needing additional attention.3. Phishing Simulation Management• Select phishing templates and attack vectors suitable for the client’s environment and user maturity levels.• Execute monthly phishing campaigns and monitor performance metrics such as click rates, report rates, and repeat offenders.• Analyze behavior patterns across departments, job roles, and risk categories.• Provide recommendations to reduce failure rates and strengthen user vigilance.4. Training Administration & Engagement Tracking• Assign cybersecurity awareness training modules based on relevance, risk, and regulatory requirements• Monitor employee training progress, overdue rates, and department level engagement trends• Work with clients to drive user participation through communication plans, reminders, and reinforcement messaging• Suggest additional or targeted training content based on observe d risks 5. Reporting & Data Analysis• Download and process data exports from the CSAT platform (Training, phishing, and risk reports)• Analyze data using tolls such as Microsoft Excel (pivot tables, formulas, visualization) • Prepare comprehensive monthly and quarterly reports that highlight:a. Performance trendsb. Human risk indicatorsc. High-risk groups and repeat offendersd. Benchmark comparisons• Deliver clear, data-driven insights in client review meetings6. Continuous Improvement & Knowledge Development• Stay updated with the latest phishing trends, social engineering tactics, and cybersecurity awareness best practices• Recommend program enhancements or additional initiatives to strengthen client security culture • Continuously improve internal templates, reporting frameworks, and delivery processes • Contribute feedback to internal team to evolve company's CSAT methodology
福利制度
Salary range: RM3,800 - RM4,000
<Leaves>
• AL: 14 days
• SL: 14 days
<Other benefits>
• Annual medical benefits
• Bonus (Depending on company performance and individual performance)
• Insurance coverage
*More details will be shared during the interview sessionMechanical Design Engineer (JB)ID:59340
5,000 MYR ~ 7,000 MYRJohor Bahru工作内容
The Mechanical Design Engineer will be responsible for design and development of automation machines and assembly lines, ensuring efficient and reliable system performance. The role requires experience in designing jigs and fixtures, pallet and carrier systems, material handling solutions, and other automation equipment, with a strong emphasis on developing innovative, efficient, and reliable automation systems.• Collaborate with business unit for DFM preparation to secure potential projects.• Coordinate with cross-functional internal teams to support design and development of automation equipment.• Design and develop Jig & Fixture, Pallet & Carrier, Material Handling System, Application Module solutions based on requirements.• Generate and manage 2D drawings, engineering documents and BOM lists.• Experienced in project management and job coordination.• Troubleshoot machine performance issues, identifying and implementing necessary improvements.• Prepare comprehensive documentation, including user manuals, FAT and SAT requirements.• Coordinate with internal stakeholders, such as electrical, software and production teams to ensure high-quality project execution.• Undertake other duties as assigned by management.
福利制度
- Phone allowance
- OT allowance
- Optical / Dental = RM300
- Medical = RM500
- Annual Leave
- Compassionate Leave
- Marriage Leave
- Travel AllowanceCrypto Quant Researcher (Strategy Builder)ID:59315
13,000 MYR ~ 16,000 MYRBukit Bintang/KLCC工作内容
About UsWe are building a next gen quantitative trading and research platform focused on systematic, data driven alpha generation across crypto markets. This is not a signal copying or indicator tuning role we want people who design, test, break, and rebuild their own strategies from first principlesRole OverviewYou will research, design, backtest, and iterate original crypto trading strategies across spot, perpetuals, and derivatives. You will work closely with engineering and trading to convert ideas into production ready systems.Key Responsibilities- Design original crypto trading strategies (momentum, mean reversion, market structure, volatility, funding, microstructure, etc.)- Build and maintain backtesting pipelines using historical crypto data (tick, OHLCV, funding, order book if available)- Perform rigorous statistical evaluation (drawdowns, regime behavior, robustness, overfitting checks)- Iterate strategies based on failure analy sis, not curve fitting- Research and engineer custom features/factors beyond standard indicators- Document strategy logic, assumptions, and failure modes clearly- Collaborate with engineers to move research into live trading systems
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Performance bonus
Other benefits will be further disclosed if shortlistedInternal Control Process Manager - HRISID:59310
12,000 MYR ~ 12,000 MYRKL Sentral工作内容
Lead the company’s internal control framework with a special focus on HRIS implementation, digital transformation, and process integration across HR, Finance & Accounting (F&A), IT, and General Affairs (GA).This is not a typical audit/internal control role — it’s a cross-functional digital governance and HR system leadership position.1.HRIS Implementation & Optimization-Lead end-to-end HRIS implementation (Core HR, Recruitment, Travel, Payroll, Performance, Talent Management, etc.).-Coordinate and manage external vendors to meet company requirements.-Collaborate with Regional HR and management to design workflows and system configurations.-Oversee data migration, testing, UAT, and go-live to ensure accuracy and smooth transition.-Continuously monitor and optimize system performance and processes.2.Project & Change Management-Develop and manage project plans, milestones, and risk mitigation strategies for HR tech projects.-Drive change management to secure user adoption and minimize disruption.-Coordinate cross-functional stakeholders and ensure accountability.-Establish governance frameworks for system enhancement and compliance.-Ensure all group companies comply with standardized processes once implemented.3.Process Improvement & Risk Management-Identify inefficiencies and risks in HR processes and propose technology-based solutions.-Ensure system settings comply with labor laws, internal policies, and data security standards.-Lead workflow automation and enhance data-driven decision-making.4.Stakeholder Collaboration & Training-Act as the primary liaison for HRIS-related projects and regional alignment.-Deliver training and documentation for HR teams and users.-Promote a digital adoption culture within HR and business units.5.Monitoring & Reporting-Build metrics and dashboards to measure HRIS performance and adoption.-Provide regular reports, insights, and recommendations to senior management.
福利制度
Basic RM12,000(Negotiable depending on your capability)
<Leaves>
Annual Leave: 18 days for the first 2 years of service
Medical Leave: 14 days for the first 2 years
Hospitalization Leave: 60 days inclusive of the sick leave Compassionate Leave: 3 days
Marriage Leave: 5 days
