63个职位: Software/Information Processing
Memory Layout Designer/LeadID:60085
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Memory Layout Designer to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Library Layout Designer/LeadID:60084
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Layout Designer to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom Layout Designer/LeadID:60083
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking an Custom Layout Designer to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDesign Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDesign Automation Engineer (Analog/Mixed-Signal IP)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSAP Consultant - (S4/HANA - FICO/PS)ID:59243
16,000 MYR ~ 25,000 MYRKota Damansara/Petaling Jaya工作内容
We are seeking a highly skilled and motivated SAP S4/HANA FICO/PS CoE Consultant to join our dynamic team. In this role, you will play a pivotal part in maintain template, driving the design, implementation, and continuous improvement of SAP solutions within our organization's finance and project systems landscape. Your expertise in SAP S4/HANA FICO (Financial Accounting and Controlling) and PS (Project Systems) will be essential in optimizing financial processes, enhancing project management capabilities, and ensuring compliance with industry regulations. This role will ensure that the CoE provides strategic direction, best practices, governance, and support for the implementation, optimization, and maintenance of these modules across the organization.Responsibilities:■ Solution Design and Implementation: Collaborate with stakeholders to gather requirements, design and configure SAP S4/HANA FICO and PS modules, and implement solutions that align with business objectives and bestpractices.■ Process Optimization: Analyze existing processes, identify inefficiencies, and propose and implement SAP-based solutions to streamline operations and improve productivity.■ Strategic Alignment: Collaborate with stakeholders to align SAP strategies with corporate objectives and long-term plans. This ensures that SAP implementations support overarching business goals and are adaptable tofuture needs.■ Continuous improvement: Stay abreast of the latest SAP technologies and industry trends, identify opportunities for improvement, and recommend and implement enhancements to optimize system performance and functionality. Stay up-to-date with the latest SAP S/4HANA releases, innovations, and industry trends, and assess their potential impact on the organization.■ Template Governance and Standards: Establish and enforce governance processes, standards, and best practices for SAP FICO/PS modules to to ensure consistency and control across all regional operations. This includes regular reviews and updates in line with evolving business and regulatory requirements. Develop and maintain documentation standards and their updates for configurations, processes.■ Compliance and Risk Management: Ensure that SAP solutions comply with relevant financial regulations and internal controls, minimizing financial risks.
福利制度
・Salary = RM 16,000 - RM 25,000 (Gross)
・AL = <2Y 15d, 2~5Y 19d, >5Y 22d
・MC = <2Y 14d, 2~5 18d, >5Y 22d
・Mobile Allowance = RM 100
・Transport Allowance = RM 450
・All business travel claimable
・Outstation Allowance (amount based on location)
・Overseas Allowance (amount based on location
・Mileage = RM 0.70 / km (within Klang Valley travel)
・Medical Claim = RM 10,000 / year (including specialist)
・Flexi Plan up to RM 1,000 (Including dental, optical, and productivity gadgets)
・Insurance: Tokio Marine (PA, Hospitalization)
・Company Activities: Annual Dinner (by division), Sport Carnival (for all Panasonic group companies)
・Mobile Phone Allowance (Upon confirmation)
・Dental, Vision, Outpatient, Group Hospitalization, etc.Sales Senior Executive / Assistant Manager (Smart Manufacturing)ID:59973
8,000 MYR ~ 12,000 MYRBukit Bintang/KLCC工作内容
We are seeking a highly motivated and results-driven Senior Sales Executive / Assistant Manager to join our industrial solutions team. In this role, you will drive revenue growth by developing new business opportunities and managing relationships with key clients. You will lead the sales cycle from prospecting to closing, ensuring that revenue and customer satisfaction goals are met.
福利制度
・Basic Salary = RM 8,000 ~ RM 12,000
※ 12K probably more senior/manager role and subject to commission or performance based
・Bonus: Around 2 months salary
※subjective, as it applies to performance based
・Cell phone allowance: RM 80 per month
・Medical claim: Maximum RM 3,200 per year
・Annual leave: 14 days
・MC: 14 days
・Company Activities: Annual Dinner, Company Trip, Team BuildingSales Senior Executive / Assistant Manager (Electrical Engineering Solutions)ID:59991
8,000 MYR ~ 12,000 MYRBukit Bintang/KLCC工作内容
Drive regional market expansion and revenue growth for high-value industrial technology portfolios. This role is responsible for delivering specialized infrastructure solutions to mission-critical environments and large-scale enterprises. The position requires a sophisticated sales approach, integrating direct high-level account management with strategic partnership development to secure long-term, complex projects.
福利制度
・Basic Salary = RM 8,000 ~ RM 12,000
・Bonus: Around 2 months salary
・Cell phone allowance: RM 80 per month
・Medical claim: Maximum RM 3,200 per year
・Annual leave: 14 days
・MC: 14 days
・Company Activities: Annual Dinner, Company Trip, Team BuildingSIPI Engineer (Senior / Staff / Principal)ID:59941
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Job SummaryResponsible for Signal Integrity and Power Integrity (SI/PI) analysis, simulation, lab validation, and customer support for high-speed digital interfaces across chip, package, and board levels.Key ResponsibilitiesSignal Integrity• Simulation for high-speed interfaces: HBM, DDR, LPDDR, UCIe, MIPI• Crosstalk, reflection, impedance, and eye-diagram analysis• Transmission line modeling and stackup reviewPower Integrity• Power delivery network (PDN) analysis and optimization• Decoupling capacitor selection and validation• PDN impedance measurement and simulation correlationTools & Methods• SI/PI tools: HyperLynx, Ansys SIwave, Cadence Sigrity• Lab equipment: TDR, VNA, high-speed oscilloscope• S-parameter, Y/Z-parameter and multi-port matrix analysis Collaboration• Work with chip, package, PCB design, and layout teams• Support customers on board design reviews and technical queries• Participate in design reviews, failure analysis, and root-cause debugging
福利制度
- Annual Leave 14 days
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
