Principal Engineer/Principal Architect (Design Verification)ID:59120

20,000 MYR ~ 30,000 MYR峇六拜 Bayan Lepas6日 ago

概述

  • 薪资

    20,000 MYR ~ 30,000 MYR

  • 产业类别

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 工作内容

    We are seeking an experienced and visionary Principal Engineer/Architect (Design Verification) to lead and drive next-generation design verification strategies, methodologies and execution. The ideal candidate will play a key technical role in shaping SkyeChip's DV architecture, methodologies, and execution frameworks to ensure world-class product quality and verification efficiency.

    Join us if you are a passionate and forward-thinking verification leader who thrives in a fast-paced, innovation-driven semiconductor environment and enjoys mentoring teams, solving complex verification challenges, and influencing design quality and other global engineering teams.

    Key Responsibilities
    1. DV Architecture and Methodology Leadership
    • Define and drive scalable, reusable, and high-efficiency DV architecture and methodology.
    • Establish verification best practices, including testbench architecture, constrained-random verification, coverage-driven methodologies, and formal verification integration.
    • Champion automation, regression management, and coverage closure frameworks for continuous efficiency improvement.

    2. Technical Strategy and Execution
    • Define verification strategies and verification plans for complex IP design verification (NOC, memory, etc.).
    • Evaluate and implement state-of-the-art tools, verification techniques, and verification accelerators.
    • Drive sign-off criteria definition, including functional and code coverage, assertions, and quality metrics.

    3. Cross-Functional Team Collaboration
    • Collaborate closely with architecture, design, software teams to ensure robust verification plans and alignment on design intent.
    • Provide technical guidance to local and global DV teams to standardize and scale best practices.

    4. Leadership and Mentoring
    • Mentor and develop technical talent within the DV team, promoting innovation and continuous learning.
    • Conduct technical reviews, training, and methodology adoption sessions.
    • Act as a key technical interface with stakeholders and management on DV efficiency and quality metrics.

资格

  • 应征条件

    • Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related field.
    • 10 to 15 years and above of experience in semiconductor Design Verification, including experience in principal technical leadership roles.
    • Strong expertise in SystemVerilog/UVM-based environments, assertion-based verification, and functional coverage methodology.
    • Hands-on experience with IP-level verification, bus protocols (AXI, AHB, APB, CHI, ACE), and verification planning.
    • Familiarity with formal verification, simulation acceleration, and coverage-driven closure strategies.
    • Proven track record in technical leading complex design verification projects and mentoring engineering teams.
    • Excellent communication and cross-functional collaboration skills.

  • 英文

    -

  • 其他语言

    English

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