概述

• 薪资

  20,000 MYR ~ 30,000 MYR

• 产业类别

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• 工作内容

  The IP Logic Design Principle Engineer will be responsible for architecting microarchitecture design implementation of an IP, spanning across all IP stack such as application layer, transaction layer, link layer, die to die layer, physical layer. Ability to code verilog / system verilog RTL for complex IP, review RTL coding, orchestra IP development phase for projects from beginning to completion. This includes the ability to technically drive the IP team on Design / Validation in completing technical tasks up to IP releases for customers. Candidate must be also capable of solving high speed timing convergence on various processes and collaborate with cross-functional teams to meet project specifications. The role will drive performance optimization and ensuring design functionality through verification and validation processes.
  
  Key Responsibilities:
  1. IP Microarchitecture Definitions
  • Define microarchitecture definition across layers and define a clean inter unit partition requirements.
  • Drive design team to deliver best-in-class IP design that optimizes for area, latency, power and performance.
  • Ability to distribute and drive the design team to implement high quality design and meeting time to market requirements.
  
  2. IP Design Responsibility
  • Implement very complicated high-speed design which can converge timing convergence at high frequency.
  • Capable of orchestrating the team on right directions of timing convergence, CDC, lintra and etc. for tools closure.
  
  3. IP Quality Responsibility
  • Review IP design and validation testplan to make sure IP Design is at top notch quality.
  
  4. IP Releases
  • Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.