Staff Design Verification Engineer (DV) / Senior Staff Design Verification Engineer (DV)ID:59121

10,000 MYR ~ 30,000 MYRBayan Lepasabout 1 month ago

Overview

  • Salary

    10,000 MYR ~ 30,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking a highly experienced and technically profound Staff Design Verification Engineer to take on a technical leadership role in pre-silicon verification for complex, next-generation Application-Specific Integrated Circuits (ASICs). This role is critical in driving verification excellence, setting technical direction, and mentoring local talent.

    Key Responsibilities
    • Verification Strategy & Ownership: Define, implement, and lead the overall verification strategy and test plan development (including functional, coverage, and performance) for complex digital ASIC blocks or full chips, ensuring robust quality before tape-out.
    • Advanced UVM Testbench: Architect, develop, and maintain advanced, reusable UVM-based verification environments using SystemVerilog to enable constrained-random and coverage-driven verification.
    • C/C++ Programming: Develop C/C++ test cases, firmware test cases for efficient hardware/software co-verification via DPI-C.
    • Execution and Triage: Hands-on execution of the verification plan, including test case development, regression management, triage, and expert root-cause analysis of functional bugs in RTL and gate-level simulations.
    • Coverage and Sign-off: Drive and achieve comprehensive functional and code coverage closure goals, utilizing advanced techniques, writing complex assertions (SVA), and ensuring formal verification compliance.
    • Technical Mentorship: Act as a subject matter expert and mentor to junior and intermediate verification engineers, fostering best practices in coding, methodology, and debug techniques across the team.
    • Flow Improvement: Evaluate, select, and develop new verification methodologies, tools, and flows (e.g., formal verification, emulation) to enhance the overall team's productivity and quality.

Qualifications

  • Requirement

    • Education: Bachelor's, Master's, or PhD degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
    • Experience: 5+ years of industry experience in pre-silicon ASIC/SoC Design Verification.
    • Technical Expertise:
    o Expert-level proficiency in SystemVerilog, UVM methodology, and SVA.
    o Expertise in C/C++ programming for developing verification test cases for co-verification.
    o Deep understanding of digital design, computer architecture (e.g., CPU cores, interconnects, high-speed interfaces), and the complete ASIC lifecycle.
    o Strong command of scripting languages, especially Python and TCL/Perl, for automation, flow development, and regression management.
    o Experience with industry-standard EDA tools for simulation, debugging, and coverage analysis.
    • Leadership & Collaboration:
    o Proven ability to independently own and drive verification projects from specification review to verification sign-off.
    o Strong analytical, problem-solving, and debugging skills.
    o Excellent communication skills for cross-functional collaboration with RTL Designers, Architects, and international partners.

  • English Level

    -

  • Other Language

    English

Additional Information

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