657 Jobs
Sales Manager (Johor)ID:59657
10,200 MYR ~ 11,200 MYRJohor BahruJob Description
We are looking for a dynamic and results-driven Sales Manager to lead and grow our Decorative Project business within Southern region. In this role, you will drive sales performance, expand market share, and lead a high-performing sales team to deliver sustainable growth in line with company objectives.This position will be based in Johor and reporting to Senior Sales Manager, Project.Job description:- Develop and execute sales strategies to achieve targets for revenue, gross margin, DSO, and market share within Southern region.- Conduct comprehensive market mapping to identify growth opportunities, monitor market trends, economic indicators, customer demand, and competitor activity.- Lead, coach, and motivate the sales team to achieve objectives, ensuring alignment with company values and culture.- Monitor daily sales activities, track performance metrics, and provide hands-on guidance to drive results.- Build and maintain strong relationships with customers, dealers, contractors, and consultants through regular site visits and project follow-ups.- Resolve customer concerns, support product application and supply matters, and ensure high levels of customer satisfaction.- Analyze monthly sales and collection reports, identify gaps, and implement corrective actions to improve performance.- Monitor collections and DSO to ensure healthy cash flow and financial discipline.- Conduct regular performance reviews and provide constructive feedback to support employee development.- Collaborate closely with internal stakeholders to ensure seamless workflow and customer-centric solutions.
Benefit
- Transport Allowance
- Mobile Claim
- Petrol Card
- Quarterly Incentive
- Annual Leave 15 days
- Medical Leave 14 days
- Medical Insurance
- Medical claim: RM5000/year for outpatient, RM40K/year for hospitalization
- Performance bonus (February)Sr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr eFUSE Design EngineerID:59655
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an eFUSE Design Engineer to own the end-to-end development of production-grade eFUSE IP on leading-edge process nodes. You will drive eFUSE array architecture, circuit design, full simulation-based verification, collateral and view generation, and quality checks — delivering robust, sign-off-ready eFUSE IP to downstream SoC integration flows. Bitcell-level design knowledge is valued; direct bitcell design experience is a plus but not required. Seniority level to be determined by experience.Key Responsibilities• Design and architect the eFUSE array circuit, including sense amplifier, reference bias, programming current control, address decoder, column multiplexer, and repair logic; ensure correct functional operation across all PVT corners.• Develop and execute comprehensive simulation plans for the eFUSE macro, covering DC/AC characterization, programming/read margin analysis, retention, endurance, and reliability corner simulations (MC, Mismatch, Aging); validate against product specifications and foundry bitcell models.• Generate and validate all required IP deliverable views and collateral: timing models (Liberty .lib), physical abstracts (LEF/GDS), behavioral models (Verilog), datasheets, and application notes; ensure consistency across all views and compliance with delivery checklist.• Define and execute IP quality checks (QC) and quality assurance (QA) regression suites; run DRC/LVS/ERC/PEX sign-off on the eFUSE macro layout; conduct formal and simulation-based functional verification; ensure all sign-off criteria are met prior to IP release.• Collaborate with the foundry and PDK team on eFUSE bitcell characterization data, SPICE models, and process design rules; translate foundry bitcell specifications and reliability requirements into array-level design constraints.• Support Testchip integration of the eFUSE macro, including test circuit design, programming and read test plan development; assist in hardware bring-up, failure analysis, and silicon–to–simulation correlation.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (General Purpose I/O) (GPIO)ID:59654
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.Key Responsibilities• Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).• Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.• Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).• Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.• Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.• Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementProposal EngineerID:59467
4,000 MYR ~ 6,000 MYRBatu KawanJob Description
1. Technical Estimation & CostingAnalyze customer-provided drawings (2D/3D CAD) to calculate required materials, machining processes, and labor hours.Determine the most competitive yet profitable pricing by understanding precision machining and sheet metal fabrication processes.2. Preparation of Technical ProposalsPropose optimal solutions using the company’s machining and automation technologies to address customer challenges, such as precision enhancement, cost reduction, or lead-time optimization.Develop specifications for customized jigs, fixtures, and automated equipment, in addition to standard products like wire shelving.3. Liaison with Customers and Internal DepartmentsCustomer Facing: Accompany the Sales team to provide technical explanations and finalize detailed specifications with clients.Internal Coordination: Conduct handover meetings with the Production and Design departments upon project award to ensure a seamless transition to manufacturing.4. Vendor & Supplier ManagementRequest quotations from external vendors for processes or material procurement that cannot be handled in-house and perform cost-benefit analysis.
Benefit
- Salary RM 4,000- RM 6,000 (depend on Experience)
- Work Time: 8:00AM to 6:00PM (Mon to Fri)
- Work Location； Batu Kawan
- AL: 10 days
- MC: 14days
- EPF,SOCSO,EIS
- Medical Allowance：RM500/year
- Commuting expenses covered：Mileage claim RM0.50/km (car), RM0.20/km (motor)
- OT fixed rate RM12/hour (basic salary > RM4k)Sales Engineer (JB)ID:59649
10,500 MYR ~ 11,000 MYRJohor Bahru, Muar, Senai, Batu Pahat, Pasir Gudang, Other Johor District, Pontian, Segamat, Tangkak, Kluang, Kota Tinggi, Kulai, Mersing, Tebrau, Iskandar Puteri, Bukit Gambir, Skudai, Nusajaya, Gelang Patah, Plentong, Pengerang, Ulu Tiram, LarkinJob Description
Role Overview:We are seeking an Outdoor Sales Engineer to drive business development in Malaysia. This is a highly field-oriented role, with the office essentially being the candidate’s car and backpack. The candidate will spend most of their time visiting customers across Johor Bahru, Selangor, and Penang on a weekly basis (e.g., one week in Johor, another in Selangor, another in Penang depending on customer activity).The main responsibility is developing new business with industrial end users, identifying opportunities, and promoting solutions directly in the field.Key Responsibilities:- Develop new business opportunities and open new accounts with industrial end users- Identify and promote solutions in the field- Build and maintain strong customer relationships- Independently manage a territory across Johor Bahru, Selangor, and Penang- Represent the company at customer meetings, industry events, and trade shows as required
Benefit
- Car Allowance
- Mobile Allowance
- Performance bonus of up to 15% of the annual base salary (based on KPI achievement)
- 13 month bonus
- Days of Annual Leave
• <2 years service: 8 days
• 2–5 years: 12 days
• >5 years: 16 days
- Sick leave
• <2 years service: 14 days
• 2–5 years: 18 days
• >5 years: 22 days
- Medical BenefitSales Engineer (KL)ID:59648
10,500 MYR ~ 11,000 MYRSentul, Kepong, Segambut, Lembah Pantai, Seputeh, Bandar Tun Razak, Cheras (KL), Bangsar, Mont Kiara, KL Sentral, Ampang, Damansara Heights, Klang, Port Klang, Ampang Jaya, USJ/Subang Jaya, Shah Alam, Cheras (Selangor), Selayang Baru, Rawang, Taman Greenwood, Seri Kembangan, Banting, Sepang, Semenyih, Chow Kit, Pudu, Seri Petaling, Other Selangor District, Other KL District, Sungai Buloh, Bukit Bintang/KLCC, Setiawangsa/Titiwangsa/Setapak/Wangsa Maju, Bandar Sunway/Puchong, Bangi/Kajang, Kota Damansara/Petaling JayaJob Description
Role Overview:We are seeking an Outdoor Sales Engineer to drive business development in Malaysia. This is a highly field-oriented role, with the office essentially being the candidate’s car and backpack. The candidate will spend most of their time visiting customers across Johor Bahru, Selangor, and Penang on a weekly basis (e.g., one week in Johor, another in Selangor, another in Penang depending on customer activity).The main responsibility is developing new business with industrial end users, identifying opportunities, and promoting solutions directly in the field.Key Responsibilities:- Develop new business opportunities and open new accounts with industrial end users- Identify and promote solutions in the field- Build and maintain strong customer relationships- Independently manage a territory across Johor Bahru, Selangor, and Penang- Represent the company at customer meetings, industry events, and trade shows as required
Benefit
- Car Allowance
- Mobile Allowance
- Performance bonus of up to 15% of the annual base salary (based on KPI achievement)
- 13 month bonus
- Days of Annual Leave
• <2 years service: 8 days
• 2–5 years: 12 days
• >5 years: 16 days
- Sick leave
• <2 years service: 14 days
• 2–5 years: 18 days
• >5 years: 22 days
- Medical Benefit