Sr eFUSE Design EngineerID:59655

10,000 MYR ~ 22,000 MYRBayan Lepasabout 7 hours ago

Overview

  • Salary

    10,000 MYR ~ 22,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking an eFUSE Design Engineer to own the end-to-end development of production-grade eFUSE IP on leading-edge process nodes. You will drive eFUSE array architecture, circuit design, full simulation-based verification, collateral and view generation, and quality checks — delivering robust, sign-off-ready eFUSE IP to downstream SoC integration flows. Bitcell-level design knowledge is valued; direct bitcell design experience is a plus but not required. Seniority level to be determined by experience.

    Key Responsibilities
    • Design and architect the eFUSE array circuit, including sense amplifier, reference bias, programming current control, address decoder, column multiplexer, and repair logic; ensure correct functional operation across all PVT corners.
    • Develop and execute comprehensive simulation plans for the eFUSE macro, covering DC/AC characterization, programming/read margin analysis, retention, endurance, and reliability corner simulations (MC, Mismatch, Aging); validate against product specifications and foundry bitcell models.
    • Generate and validate all required IP deliverable views and collateral: timing models (Liberty .lib), physical abstracts (LEF/GDS), behavioral models (Verilog), datasheets, and application notes; ensure consistency across all views and compliance with delivery checklist.
    • Define and execute IP quality checks (QC) and quality assurance (QA) regression suites; run DRC/LVS/ERC/PEX sign-off on the eFUSE macro layout; conduct formal and simulation-based functional verification; ensure all sign-off criteria are met prior to IP release.
    • Collaborate with the foundry and PDK team on eFUSE bitcell characterization data, SPICE models, and process design rules; translate foundry bitcell specifications and reliability requirements into array-level design constraints.
    • Support Testchip integration of the eFUSE macro, including test circuit design, programming and read test plan development; assist in hardware bring-up, failure analysis, and silicon–to–simulation correlation.

Qualifications

  • Requirement

    • BS/MS in Electrical/Electronic Engineering or related discipline (or equivalent industry experience).
    • 5–12+ years of analog/mixed-signal or custom IC design experience; prior hands-on experience designing eFUSE macros or NVM-type IP (OTP, eFUSE, MRAM, Flash controller) is strongly preferred.
    • Solid understanding of eFUSE/OTP bitcell operation principles (programming physics, read mechanism, retention and endurance); direct bitcell design experience is a plus, but is not a requirement — candidate must be comfortable consuming and interpreting foundry bitcell SPICE models and characterization data.
    • Strong transistor-level analog/mixed-signal circuit design skills: sense amplifiers, reference generators, bandgap/bias circuits, level shifters, ESD-aware I/O, and high-voltage programming circuits.
    • Proficiency with Cadence Virtuoso (schematic entry and simulation), HSPICE or Spectre for circuit-level simulation; experience running Monte Carlo, worst-case corner, and mismatch analyses for yield estimation.
    • Hands-on experience generating IP deliverable collateral: Liberty timing models (.lib), LEF physical abstracts, behavioral Verilog models, and datasheet documentation; familiarity with IP release and handoff processes.
    • Experience with physical verification sign-off (DRC/LVS/ERC/PEX) using Calibre or equivalent; ability to review and guide custom layout for EM/IR compliance.
    • Scripting proficiency (Python, Tcl, Perl, or SKILL) for simulation automation, results post-processing, and regression management.

    Preferred / Nice-to-Have Experience
    • Direct experience designing eFUSE or OTP bitcells (silicide-fuse, poly-fuse, gate-oxide breakdown, or antifuse type) at the transistor level is a significant advantage.
    • Exposure to silicon validation of eFUSE or NVM macros, including programming yield, read margin distribution analysis, and post-silicon model correlation.
    • Familiarity with high-voltage (HV) design rules, ESD protection strategies, and latch-up prevention in advanced CMOS processes.
    • Experience with IP integration into SoC flows (synthesis, place-and-route handoff); understanding of how eFUSE macros interact with OTP controller RTL, redundancy and repair schemes, and security/encryption use cases (e.g., key storage, trim bits, die ID).

  • English Level

    -

  • Other Language

    English

Additional Information

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