41 Jobs: Job Vacancies for Bandar Sunway/Puchong Area
Sr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSales Engineer (KL)ID:59648
10,500 MYR ~ 11,000 MYRSentul, Kepong, Segambut, Lembah Pantai, Seputeh, Bandar Tun Razak, Cheras (KL), Bangsar, Mont Kiara, KL Sentral, Ampang, Damansara Heights, Klang, Port Klang, Ampang Jaya, USJ/Subang Jaya, Shah Alam, Cheras (Selangor), Selayang Baru, Rawang, Taman Greenwood, Seri Kembangan, Banting, Sepang, Semenyih, Chow Kit, Pudu, Seri Petaling, Other Selangor District, Other KL District, Sungai Buloh, Bukit Bintang/KLCC, Setiawangsa/Titiwangsa/Setapak/Wangsa Maju, Bandar Sunway/Puchong, Bangi/Kajang, Kota Damansara/Petaling JayaJob Description
Role Overview:We are seeking an Outdoor Sales Engineer to drive business development in Malaysia. This is a highly field-oriented role, with the office essentially being the candidate’s car and backpack. The candidate will spend most of their time visiting customers across Johor Bahru, Selangor, and Penang on a weekly basis (e.g., one week in Johor, another in Selangor, another in Penang depending on customer activity).The main responsibility is developing new business with industrial end users, identifying opportunities, and promoting solutions directly in the field.Key Responsibilities:- Develop new business opportunities and open new accounts with industrial end users- Identify and promote solutions in the field- Build and maintain strong customer relationships- Independently manage a territory across Johor Bahru, Selangor, and Penang- Represent the company at customer meetings, industry events, and trade shows as required
Benefit
- Car Allowance
- Mobile Allowance
- Performance bonus of up to 15% of the annual base salary (based on KPI achievement)
- 13 month bonus
- Days of Annual Leave
• <2 years service: 8 days
• 2–5 years: 12 days
• >5 years: 16 days
- Sick leave
• <2 years service: 14 days
• 2–5 years: 18 days
• >5 years: 22 days
- Medical BenefitProject Manager (Game Operations)ID:59626
5,000 MYR ~ 6,500 MYRSeri Petaling, Bandar Sunway/Puchong, Kota Damansara/Petaling JayaJob Description
The Project Manager will be the vital link between game developers and our internal technical teams, ensuring that platform features and game integrations are delivered on time and to the highest standard across the SEA and Greater China markets.Key Responsibilities1. Project Tracking:• End-to-end monitoring of development progress for critical platform features, including Payment Gateways, SDKs, and Account Systems.2. Game Onboarding:• Act as the primary bridge between external developers and the internal tech team to ensure seamless game integration.3. Operational Reporting:• Monitor and analyze key platform KPIs (DAU, ARPU, Retention) and prepare insightful reports to drive performance improvements.4. Regional Localization:• Coordinate and oversee L10n (localization) tasks specifically for the South East Asia market (MY, PH, TH), ensuring cultural relevance and quality control.
Benefit
- Annual Leave: 14 days
- Medical Leave: 14 days
- Parking allowance: RM100
- Medical and dental claims: RM2000/year
- Medical insurance
- Performance bonusSupply Chain ExecutiveID:59606
3,000 MYR ~ 4,500 MYRBandar Sunway/PuchongJob Description
■ ORDER PROCESSING・Receive and review customer orders for accuracy and completeness.・Confirm order details with customer and sales division including product specifications, quantities, and delivery addresses.・Enter orders into accounting system and generate customer order ■ INVENTORY & STOCK ALLOCATION ・Check inventory levels to ensure sufficient stock availability for the order.・Allocate stock from the warehouse or restocking if necessary.■ ORDER PLANNING・Allocate stock for open orders for delivery/shipment planning to update customer and sales division・Create proforma invoice based on order details for customer advance payment・Follow up with the finance department, customers, or sales division to ensure timely payment.■ SHIPPING PROCESSING・Prepare goods for shipment by coordinating with the warehouse for packing and labelling.・Ensure that all required shipping documents, such as Bills of Lading, Commercial Invoices, Packing Lists and other require documents are prepared and accurate.・Select appropriate shipping methods and carriers based on freight cost estimation, delivery timelines, and customer requirements.・Schedule shipments and communicate with freight forwarders, couriers, or transportation companies.・Monitor shipment progress and provide tracking information to customers.・Resolve any shipping issues, delays, or discrepancies promptly, ensuring a smooth delivery process.・Confirm delivery with the customer and address any post-delivery issues or complaints.・Maintain records of shipments for future reference and auditing purposes.・Ensure all documents related to the export process are kept for finance, audit or compliance.■ IMPORT CUSTOMS CLEARANCE・Upon received Supplier import alert and shipping documents, check import document details against Supplier purchase order.・Send import clearance instruction, shipping documents, serial number and HS code to import handling agent and warehouse receiving.・Perform goods received in accounting system once the goods are transported to warehouse or another designated location.・Report to Supplier if the goods are damage or dispute in item or quantity against the purchase order and shipping documents.・Arrange appointed insurance agent for inspection for damage goods if require・Update Inventory data for stock allocation planning・Ensure all documents related to the import process are kept for finance, audit or compliance■ INVENTORY RECONCILIATION・Verify received goods against stock levels and warehouse system to ensure accuracy and update inventory record accordingly.・Monitor reorder points and replenish stock as needed to maintain optimal inventory levels.
Benefit
- Basic Salary = RM 4,000 ~ RM 5,000
- AL : >1Y 14d, >2Y 16d
- MC : <2Y 14d, 2~5Y 18d, >5Y 22d
- 60 days of paid hospitalization leave.
- Paternity Leave 2 days, marriage leave 2 days
- All business travel expenses claim reimbursement basis.
- Medical Claim : Max RM 1,000 p/a by medical cert
(excluding optical, dental, specialist, plastic surgery & etc)
- Bonus : Twice a year. (July & Dec), depend on performance, past year around 3 months annually
- Increment rate = Averagely 6%Site Supervisor (Interior Design)ID:58202
3,500 MYR ~ 5,000 MYRBandar Sunway/PuchongJob Description
< Job Summary >You will play a crucial role in overseeing the day-to-day operations and execution of residential and commercial construction projects.This is a full-time position that requires strong leadership, technical expertise and a commitment to ensuring the successful delivery of our construction projects.< Job Scopes >・Effectively manage and coordinate the activities of construction workers, tradesmen and sub-contractors to ensure projects are completed on time, within budget and to the required quality standards.・Monitor project progress and provide regular updates to the project management team.・Ensure compliance with all relevant construction regulations and company policies.・Identify opportunities for process improvements and implement effective solutions.・Execute & coordinate site activities.・Assist the project manager in preparing daily progress report, planning project and creating schedule.・Materials handling and recordings.・Monitor site plant & machinery.・Participate in site meeting, review and check construction drawings.・To liaise with sub-contractor and consultants to ensure all works are carried as per drawings and specification.
Benefit
・Basic Salary = RM 3,500 ~ RM 5,000
・AL/MC = 14 days
・Flexi Benefits = RM 200 (For dental claim, optometry claim) ** after confirmation
・All business travel expenses are claimable
・Season car park provided
・CNY, Hari Raya, Deepavali Dinner
・Bonus subject to performance, paid out before CNY
・Increment based on performanceSr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
