63 Jobs: Job Vacancies for Other(Electrical/Semi-Conductor) Engineer Positions
Production SupervisorID:60570
5,000 MYR ~ 6,000 MYRBayan LepasJob Description
• Oversee the daily production processes for PCBA and SMT lines to ensure efficiency, quality, and timely delivery of products. • Collaborate with cross-functional teams to troubleshoot and resolve production issues, ensuring minimal downtime and maximum productivity. • Implement and optimize manufacturing processes to improve yield, reduce costs, and enhance product quality. • Support new product introductions (NPI) by setting up and validating new processes and equipment. • Monitor production data and KPIs to identify areas for improvement, and drive continuous improvement initiatives. • Lead root cause analysis and corrective actions for process and equipment-related issues. • Ensure compliance with industry standards and company policies, including safety and quality requirements. • Ensure all Operators and line leaders are certified all time. Provide trainings and drive multiskills maturity. • Manage and control production indirect material usage.
Benefit
Salary: RM5,000 - RM6,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)Service Engineer (Shah Alam) ID:60508
3,500 MYR ~ 4,500 MYRShah AlamJob Description
• Execute machine and system installation, commissioning, and performance verification to ensure successful deployment• Carry out maintenance, troubleshooting, repair, and servicing activities to ensure optimal machine performance and reliability• Provide technical guidance and support to customers, addressing operational issues and recommending appropriate solutions• Perform validation of machine performance at customer site • Handle customer inquiries for servicing, general service ,repair work, quotation, and parts replacement
Benefit
Salary range: RM3,500 - RM4,500
<Allowances>
• Car allowance (depending on the car's value and condition, i.e. less or more than 10 years, less or more than 60K)
<Other benefits>
• AL: Start with 12 days
• SL:14 days
• Medical benefit claimable
• Insurance: Hospitalization, PA insurance, and more
• Annual medical checkup
• Uniform/Laptop/Mobile phone will be provided
• Entitled to incentive is achieved target
• Petrol card will be provided (home to office and client place)
• Annual bonus
• Parking/Tolls - ClaimableTool Design Engineer (Stamping)ID:60454
3,860 MYR ~ 5,360 MYRBukit MinyakJob Description
- Provide new material spec., Tooling information, Design checklist, DFMEA.- New tool design layout and drawings.- Participate in new tool assembly and debugging tool.- Involved in improvement project and modification tool with Die Maintenance Department.- To order standard part and follow up delivery lead time according to tooling schedule.- Involve in vendor fabrication quality issue and delivery issue to meet the tooling schedule.- Review of FA report and follow-up on sample submission.- Participate in transfer tooling project for buy off.- To handle other tasks and duties as and when requested by superior.
Benefit
- AL: 12 days, increase gradually based on company policy.
- Individual Insurance
- Medical RM200/year & Dental RM300/year
- Toll claimable (Candidate from Island only)
- Mobile allowances (Depend)
- Individual bonus - 1month fixed
- Increment every year (July) -Rate based on performanceMechanical Design Engineer (Senior/Team Lead) (JB)ID:58970
8,000 MYR ~ 15,000 MYRJohor BahruJob Description
Core Duties:1. Responsible for project design and planning.2. Drafting technical drawings and preparing related documentation.3. Managing drawings and design documents.4. Troubleshooting design issues during product trial production.Job Responsibilities1. Project design and planning.2. 3D design for projects.3. Preparation of 2D drawings, BOMs, operation manuals, and maintenance manuals. 4. Drafting other technical documentation.5. Organizing, compiling, and archiving project materials.
Benefit
- Annual Leave starting from 10 days
- Phone allowance
- OT allowance
- Optical / Dental = RM300
- Medical = RM500
- Compassionate Leave
- Marriage Leave
- Travel AllowanceDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment【Fresh Grads Ok!】 Quality EngineerID:60220
5,000 MYR ~ 8,000 MYRBayan LepasJob Description
This role is responsible for ensuring product quality through inspections, issue resolution, corrective actions, and continuous improvement across manufacturing processes.• Responsible for quality management, quality inspection and quality control during the manufacturing process.• Propose and implement corrective and preventative actions and track their effectiveness shall potential issue arise.• Assist in quality analysis of product quality issues, execute and implement quality improvement plans, track quality improvement plans, track quality improvements and ensure the final resolution of quality issues.• Summarize and analyze various quality data and push responsible departments to resolve issues promptly.• Handle customer complaints, drive improvements and track the effectiveness of corrective actions.• Collaborate with project and technical personnel on new product pilot runs and quality control.• Any ad-hoc tasks as per assigned by manager.
Benefit
Salary: RM5,000 - RM8,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)Physical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Test Operations Engineer ID:60157
6,417 MYR ~ 9,167 MYRBayan LepasJob Description
【Job description】This position is expected to provide Test Operations and Engineering support for products post manufacturing release and deliver operational excellence through cost reductions, OEE, yield and cycle time improvements to achieve our test KPI goals with our Test Manufacturing Sites (Internal and Outsourcing Suppliers) in Malaysia, Thailand, Singapore and across Asia (Taiwan, China, Korea). This position reports into Operations Engineering Department (OED).【Key Responsibilities】- Responsible for Test Operations interface to Renesas Product Groups and other functional teams (Supply Chain, Quality, Packaging, Foundry, PMO) across US, Japan, India, Malaysia, and China on all phases of product lifecycle- Execute daily test operations activities with internal factories and test OSATs to ensure customer delivery fulfillment (i.e. Lot tracking and dispositions, Test Program releases, Hardware Troubleshooting/Repairs, Equipment up-time, Tester Utilization OEE tracking, Continuous Improvement Process, etc)- Coordinate Probe/Final Test transfer from New Product Introduction to High Volume Manufacturing from Renesas Product Group groups- Execute new test capacity expansions (tester/ handler/ hardware) to ensure sufficient capacity and meet production demand- Deployment of new tester/handler technology and test solutions to test manufacturing sites from test development- Implement best known practices and process within test manufacturing sites- Drive Gross Margins (OEE, Yield, Retest) improvement initiatives
Benefit
Annual Salary Range ::RM77000-RM110000
(Monthly: RM6,417-RM9,167)
*Regarding the employee benefits, please check them directly with the company during your interview.Memory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment