67 Jobs: Job Vacancies for Other(Electrical/Semi-Conductor) Engineer Positions
Sr Staff Product EngineerID:60156
13,025 MYR ~ 18,608 MYRBayan LepasJob Description
【Job description】Analog and Mixed Signal Business Unit (AMS) is looking for a Snr Staff Product Engineer to join our team to drive the product development of state-of-the-art products. This is a unique and exciting opportunity to work with a cross-functional team to bring a product to volume production starting from product conception to production release. The job scope includes but is not limited to, development of the test plan to ensure datasheet specifications are met. Own the qualification plan and the execution to comply with various JEDEC/AEC quality standards. Own product quality assessment through reliability tests. Collaborate with multi-functional teams such as Design, Test, Applications and Failure Analysis teams during first silicon debug and to root cause field failures. Creation and maintenance of product BOM. Monitor production data to address yield and quality deficiencies using statistical analysis.【Key Responsibilities】• Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers• Provide support for DfT, Product releases and Qualifications in Penang• Compliance to Jedec and AEC standards• Datasheet and automotive compliance reports• Real time customer support for design, product and quality related issues• Temperature/Voltage/Process characterization and production limit setting• Product new product introduction and yield ownership• Product BOM release and maintenance• Excursion management for both suppliers and customers• Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams• KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times• PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste
Benefit
Annual Salary Range ::RM130100-RM185800
(Monthly: RM10,842-RM15,483)
*Regarding the employee benefits, please check them directly with the company during your interview.Staff Hardware Test EngineerID:60155
10,842 MYR ~ 15,483 MYRBayan LepasJob Description
【Job description】The Hardware Test Engineer is responsible for driving ATE test solutions for devices and module roadmap and solutions for Our company’ AI-focused semiconductor portfolio. The position plays a critical role in ensuring product delivery ensuring robust backend solution with no quality issues for AI power semiconductors supporting data center, accelerator, and advanced computing applications.【Key Responsibilities】- Project manage the design and logistics of ATE hardware (load boards, probe cards, test sockets and change kits) from definition, RFQ, design review and approval to NPI or Production Release.- Main contact with ATE hardware vendors for technical, commercial and operational aspects.- Manage and monitor spending budget for ATE hardware,- Manage and maintain the tool/system for ATE hardware request and tracking hardware inventory.- Identify and execute areas for Gross Margin Improvement Initiatives in areas related to load boards, probe cards, test sockets, change kits.- Interface with cross-functional (Product Group’s engineering, operation etc.) teams for forecast on ATE hardware and execute to support NPI timeline, revenue and capacity- Technical expertise in module testing (socket, board, change kit and handling) on ATE/handlers and providing technical direction for production solution
Benefit
Annual Salary Range ::RM130100-RM185800
(Monthly: RM10,842-RM15,483)
*Regarding the employee benefits, please check them directly with the company during your interview.Logic Design Verification EngineerID:60088
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking to hire Logic Verification Engineer. Familiarity with LPDDR and HBM memory interface IP will be a plus. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain UVM-based verification environments for various IPs, including constrained-random testbenches, protocol-aware monitors, scoreboards, and checkers.• Author detailed verification plans based on specifications, architectural documents, and use-case scenarios; own coverage closure end-to-end.• Drive coverage-driven verification (CDV): functional coverage (covergroups/coverpoints), code coverage (statement, branch, toggle), and SystemVerilog assertions (SVA); identify gaps and close with targeted test scenarios.• Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis; apply Formal Property Verification (FPV) to prove critical design properties.• Debug simulation failures in collaboration with RTL designers; document results, coverage metrics, and regression summaries for traceability and sign-off.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDFT Logic Design EngineerID:60087
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a DFT Logic Design Engineer to implement testability infrastructure across our digital IP portfolio. You will define DFT strategy, integrate scan and BIST structures at the RTL level, and drive fault coverage from early design through silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Define and own the DFT architecture for digital and mixed-signal blocks: scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, and MBIST/LBIST planning; document and maintain the DFT specification throughout the design cycle.• Develop and integrate DFT RTL (SystemVerilog/Verilog): scan wrappers, BIST controllers, test access ports, and clock/reset control logic; ensure DFT structures are synthesis-clean, timing-closed, and do not degrade functional performance or power.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets; achieve and sign off on target fault coverage metrics agreed with the test engineering team.• Collaborate with RTL designers on DFT-aware coding guidelines; perform DFT rule checking, CDC analysis, and Lint to identify and resolve testability violations early in the design cycle before netlist handoff.• Support physical design handoff: provide scan chain ordering recommendations, validate DFT netlist post-layout (LEC, STA), and resolve DFT-related ECOs during timing closure and tapeout.• Support post-silicon validation and ATE bring-up: work with test engineers to load and debug ATPG patterns on ATE platforms, analyze yield data, and triage failing patterns back to root-cause RTL or physical design issues.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout Designer/LeadID:60085
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Designer to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Library Layout Designer/LeadID:60084
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Designer to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom Layout Designer/LeadID:60083
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking an Custom Layout Designer to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDesign Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDesign Automation Engineer (Analog/Mixed-Signal IP)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
