Memory Layout Designer/LeadID:60085

8,000 MYR ~ 16,000 MYRBayan Lepasabout 8 hours ago

Overview

  • Salary

    8,000 MYR ~ 16,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking a Memory Layout Designer to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.

    Key Responsibilities
    • Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.
    • Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.
    • Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.
    • Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.
    • Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.
    • Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.
    • Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.

Qualifications

  • Requirement

    • BS/MS in Electrical/Electronic Engineering (or equivalent experience).
    • 3-5 years of hands-on full-custom physical layout experience in memory design (SRAM and/or RF).
    • Proficient with any layout entry EDA tool such as Cadence Virtuoso Layout Suite (or equivalent) and physical verification tools (Calibre DRC/LVS or equivalent); able to resolve violations independently to tape-out quality.
    • Solid working knowledge of CMOS process design rules at advanced nodes (28nm and below); ability to interpret and apply complex DRM constraints in day-to-day layout execution.
    • Ability to read and understand transistor-level schematics; clear grasp of the layout-tocircuit relationship covering parasitics, device matching, IR drop, and latch-up.
    • Hands-on experience with parasitic extraction flows (Calibre PEX, Quantus, or StarRC) and back-annotation of extracted netlists to circuit simulation.
    • Demonstrated ability to take a memory macro from initial floorplan through full DRC/LVS sign-off with minimal supervision.

    Preferred / Nice-to-Have Experience
    • Experience as part of a Memory Compiler team; familiarity with modular layout design requirements to feed automated compiler generation flows (e.g., parameterized cell banks, snap-to-grid floorplans, compiler-consumable GDS/LEF hierarchies).
    • Awareness of Memory Compiler output views and their layout constraints: LEF pin/obstruction abstraction, GDS layer mapping, and stream-out requirements.
    • Exposure to EM/IR analysis and memory macro power integrity sign-off methodology.
    • Experience with FinFET-node layout constraints: fin quantization, local interconnect rules, self-aligned multi-patterning (SAMP/SADP), and via-pillar requirements.
    • Layout automation scripting (Cadence SKILL, TCL, Python, or equivalent) for repetitive tasks such as array generation, via-bar insertion, or DRC waiver management. Scripting proficiency is a bonus, not a requirement.

  • English Level

    -

  • Other Language

    English

Additional Information

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