Standard Cells Library Layout Designer/LeadID:60084

8,000 MYR ~ 16,000 MYRBayan Lepasabout 10 hours ago

Overview

  • Salary

    8,000 MYR ~ 16,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking a Standard Cells Library Layout Designer to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.

    Key Responsibilities
    • Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.
    • Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.
    • Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.
    • Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.
    • Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.

Qualifications

  • Requirement

    • BS/MS in Electrical/Electronic Engineering (or equivalent experience).
    • 3–5 years of hands-on IC layout experience, with direct exposure to standard cell or full-custom digital cell layout; experience on at least one sub-28nm process node is preferred.
    • Proficiency in Cadence Virtuoso for full-custom transistor-level layout; comfortable navigating PDK layer stacks, device PCells, and design rule constraints without hand-holding.
    • Practical DRC/LVS verification experience using Calibre or equivalent; able to read error reports, cross-probe violations in layout, and resolve them independently for routine rule categories (min width, spacing, enclosure, EOL, via density).
    • Good working knowledge of cell boundary rules: CPP-grid alignment, N-well/P-well continuity, dummy poly, and power rail connections required for correct row-based abutment.
    • Basic familiarity with parasitic extraction concepts; able to review a PEX netlist with guidance and understand how layout geometry choices affect RC parasitics on critical nets.
    • Ability to read and work from circuit schematics (CDL/SPICE), cell specifications, and foundry DRM documentation; self-directed and able to deliver completed cell layouts on schedule with minimal day-to-day guidance.

    Preferred / Nice-to-Have Experience
    • Exposure to FinFET layout (12/7/5/3nm). Familiarity with fin patterning, gate-cut rules, and local interconnect layers is a plus.
    • Experience with Cadence SKILL or basic Tcl/Python scripting for simple layout utilities (e.g., layer selection, repetitive drawing tasks) is a plus.
    • Familiarity with DFM best practices: via redundancy, recommended-rule compliance, and litho-friendly routing patterns is a plus.
    • Exposure to LEF abstract generation and basic understanding of how cell pin shapes and obstructions affect P&R routability is advantageous.
    • Support standard cell library IP integration into Testchip: assist in layout assembly of library validation structures, GDS streaming, and provide layout debug support during hardware bring-up as required.

  • English Level

    -

  • Other Language

    English

Additional Information

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