70个职位: 招聘信息 工程师(IT/互联网/电信)
Backend EngineerID:60573
7,000 MYR ~ 9,000 MYRKota Damansara/Petaling Jaya工作内容
• Design and develop scalable backend systems and RESTful APIs.• Build and maintain server-side application logic.• Integrate with databases, third-party services, and external systems.• Optimize system performance, scalability, and security.• Design and maintain database schemas and ensure data integrity.• Troubleshoot and resolve backend-related issues in development and production environments.• Participate in system architecture design and technical documentation.• Collaborate with frontend developers, system analysts, and cross-functional teams.• Mentor junior developers and conduct code reviews to maintain coding standards.
福利制度
Salary range: ~RM7,000 - RM9,000
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activitiesIT - Assistant Manager (Melaka)ID:60396
5,000 MYR ~ 6,500 MYRMalacca工作内容
[Summary]Lead and manage the company's IT infrastructure, security, operations, and technology projects to ensure stable, secure, and efficient business operations. Oversee IT resources, vendors, and team development while driving continuous improvement and compliance.[Job Responsibilities]- Manage and maintain the company's IT infrastructure, including networks, servers, systems, and end-user devices.- Ensure system stability, performance, availability, and timely software and security updates.- Implement and strengthen IT security measures to protect company systems, networks, and data.- Manage data backup, cybersecurity monitoring, threat prevention, and security compliance.- Oversee daily IT operations and provide technical support to ensure business continuity.- Troubleshoot and resolve IT-related issues in a timely manner, including critical incidents and emergencies.- Plan, manage, and execute IT projects and system improvement initiatives.- Coordinate with external vendors and service providers to support business and technology requirements.- Ensure compliance with company policies, SOPs, legal regulations, and IT governance standards.- Manage IT budgets, resource allocation, manpower planning, and cost optimization initiatives.- Lead, coach, and develop IT team members through training, performance management, and career development.- Identify and recommend new technologies and process improvements to enhance operational efficiency and business performance.
福利制度
- Meal Allowance
- Transportation Allowance
- Parking Allowance
- Company laptop and phone provided
- Company Car provided (for Business trips)
- OT: 1.5 times of normal hourly pay
- Salary Increment
- Company Trip
- Bonus
- Replacement Leave (business events are falls on Sat, Sun or PH)
- Annual Leave
- Medical Leave
- EPF, SOCSO
- InsuranceSenior Software Engineer (C/C++) - PGID:60301
12,000 MYR ~ 15,000 MYRGeorgetown工作内容
- Design, develop, and optimize high-performance trading systems in C++/ C.- Collaborate with traders and engineers to implement new strategies and features.- Work on low-latency networking, real-time data processing, and system reliability.- Contribute to architectural decisions and performance tuning.
福利制度
- AL: starting from 15 days
- MC: starting from 14 days
- EPF, SOCSO, EIS
- Performance bonus
- Paid vacation and daily lunch provided
- Medical, vision and dental coverage
- Health Insurance
- Car park subsidySenior Software Engineer (C/C++) - KLID:60300
12,000 MYR ~ 15,000 MYRDamansara Heights工作内容
- Design, develop, and optimize high-performance trading systems in C++/ C.- Collaborate with traders and engineers to implement new strategies and features.- Work on low-latency networking, real-time data processing, and system reliability.- Contribute to architectural decisions and performance tuning.
福利制度
- AL: starting from 15 days
- MC: starting from 14 days
- EPF, SOCSO
- Performance bonus
- Paid vacation and daily lunch provided
- Medical, vision and dental coverage
- Health Insurance
- Car park subsidyDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior UI DesignerID:60099
6,000 MYR ~ 10,000 MYRBangsar工作内容
We are seeking a highly skilled and experienced UI/UX Designer to lead the design of intuitive, engaging, and aesthetically appealing digital experiences across web, mobile, and emerging platforms. As a member of the design team, you will collaborate closely with product managers, engineers, and stakeholders to shape the user journey and define the visual language of our products.Key Responsibilities- Lead end-to-end design process: research, ideation, wireframing, prototyping, UI design, and usability testing.- Translate complex business requirements into intuitive and elegant user-centered solutions.- Create and maintain design systems, UI libraries, and style guides.- Champion UX best practices and advocate for user needs in product planning.- Conduct user research and usability studies to iterate and validate designs.- Collaborate with cross-functional teams to ensure high-quality implementation of designs.
福利制度
Annual Leave:
1-2 years = 12 days
3-4 years = 16 days
5 years and above = 18 days
Bonus:
13th month salary
Allowances:
Transport, Meal, Birthday Allowance
Medical/Dental/Optical claim
Others:
- Sports Activities (Badminton & Basketball)
- Company Outing
- Training and certification sponsored by company (Selected employees).
- Rewards and recognition: Long Service Award / Best Performer Award / Role Model Awards etc
- Project Incentive (upon Company Declaration based on project performance)Memory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment