【招聘结束】 Senior Staff IP Logic Design / MicroarchitectID:59122

该职位的招聘已结束

15,000 MYR ~ 22,000 MYR峇六拜 Bayan Lepas3个月以上前

概述

  • 薪资

    15,000 MYR ~ 22,000 MYR

  • 工作行业

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 工作内容

    The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.

    Key Responsibilities:
    1. IP Design Responsibility
    • Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.
    • Ability to drive a low power and complex design to completions.

    2. IP Quality Responsibility
    • Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.

    3. IP Releases
    • Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.

资格

  • 任职资格

    • Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field.
    • Minimum 10 year’s experience in high-speed digital logic design in the semiconductor industry.
    • Strong skills in Logic Design and RTL Coding with Verilog or system Verilog.
    • Experience in high-speed timing convergence in various process node.
    • Deep understanding of Computer Architecture, memory traffic, io controller such as PCIe or UCIe.
    • Excellent problem-solving abilities and attention to details.
    • Ability to work collaboratively with cross-functional teams for project completions.
    • Ability to execute various IP design tools such as CDC, Lintra, FEV, etc.

  • 英文

    -

  • 其他语言

    English

附加信息

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