Overview

• Salary

  10,000 MYR ~ 22,000 MYR

• Industry

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• Job Description

  We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.
  
  Key Responsibilities
  • Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.
  • Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.
  • Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.
  • Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.
  • Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).
  • Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.
  • Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.
  • Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.
  • Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.
  • Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.
  • Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.