42 Jobs: Manufacturing(Computer/Telecommunication)
NoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan BaruJob Description
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Expert System Board Design EngineerID:58749
10,000 MYR ~ 40,000 MYRBayan LepasJob Description
• Lead the end-to-end development of complex multilayer system boards, including architecture definition, schematic design & technical decision-making.• Drive component selection, trade-off analysis & architecture optimization to meet electrical, thermal, and mechanical constraints.• Ensure high-speed signal integrity, power integrity & EMI/EMC compliance through simulation, design & testing.• Lead board bring-up, root cause analysis, and system-level debug using lab instruments (oscilloscopes, logic analyzers, spectrum analyzers, etc.).• Define test strategies and validate hardware against functional, environmental, and reliability requirements.• Prepare and review detailed design documentation: schematics, BOMs, layout constraints, test reports, and manufacturing files.• Collaborate with PCB layout engineers on components placements, routing and PCB stack up.• Skilful on handing rework tool to preforming board rework and modifications to hardware components.• Collaborate with cross-functional teams including SoC, firmware, packaging, mechanical, and manufacturing teams.• Interface with suppliers, PCB fabrication and assembly vendors for prototyping and production.• Provide technical leadership, mentoring, and code/design reviews for junior team members.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design / MicroarchitectID:59122
15,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to drive a low power and complex design to completions.2. IP Quality Responsibility• Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.3. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStaff/Senior Staff/Principal Design Verification Engineer (DV)ID:59121
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a highly experienced and technically profound Staff Design Verification Engineer to take on a technical leadership role in pre-silicon verification for complex, next-generation Application-Specific Integrated Circuits (ASICs). This role is critical in driving verification excellence, setting technical direction, and mentoring local talent.Key Responsibilities• Verification Strategy & Ownership: Define, implement, and lead the overall verification strategy and test plan development (including functional, coverage, and performance) for complex digital ASIC blocks or full chips, ensuring robust quality before tape-out.• Advanced UVM Testbench: Architect, develop, and maintain advanced, reusable UVM-based verification environments using SystemVerilog to enable constrained-random and coverage-driven verification.• C/C++ Programming: Develop C/C++ test cases, firmware test cases for efficient hardware/software co-verification via DPI-C.• Execution and Triage: Hands-on execution of the verification plan, including test case development, regression management, triage, and expert root-cause analysis of functional bugs in RTL and gate-level simulations.• Coverage and Sign-off: Drive and achieve comprehensive functional and code coverage closure goals, utilizing advanced techniques, writing complex assertions (SVA), and ensuring formal verification compliance.• Technical Mentorship: Act as a subject matter expert and mentor to junior and intermediate verification engineers, fostering best practices in coding, methodology, and debug techniques across the team.• Flow Improvement: Evaluate, select, and develop new verification methodologies, tools, and flows (e.g., formal verification, emulation) to enhance the overall team's productivity and quality.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPrincipal Engineer/Principal Architect (Design Verification)ID:59120
20,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced and visionary Principal Engineer/Architect (Design Verification) to lead and drive next-generation design verification strategies, methodologies and execution. The ideal candidate will play a key technical role in shaping DV architecture, methodologies, and execution frameworks to ensure world-class product quality and verification efficiency.Join us if you are a passionate and forward-thinking verification leader who thrives in a fast-paced, innovation-driven semiconductor environment and enjoys mentoring teams, solving complex verification challenges, and influencing design quality and other global engineering teams.Key Responsibilities1. DV Architecture and Methodology Leadership• Define and drive scalable, reusable, and high-efficiency DV architecture and methodology.• Establish verification best practices, including testbench architecture, constrained-random verification, coverage-driven methodologies, and formal verification integration.• Champion automation, regression management, and coverage closure frameworks for continuous efficiency improvement.2. Technical Strategy and Execution• Define verification strategies and verification plans for complex IP design verification (NOC, memory, etc.).• Evaluate and implement state-of-the-art tools, verification techniques, and verification accelerators.• Drive sign-off criteria definition, including functional and code coverage, assertions, and quality metrics.3. Cross-Functional Team Collaboration• Collaborate closely with architecture, design, software teams to ensure robust verification plans and alignment on design intent.• Provide technical guidance to local and global DV teams to standardize and scale best practices.4. Leadership and Mentoring• Mentor and develop technical talent within the DV team, promoting innovation and continuous learning.• Conduct technical reviews, training, and methodology adoption sessions.• Act as a key technical interface with stakeholders and management on DV efficiency and quality metrics.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCircuit Design Manager / Senior ManagerID:59119
15,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery• Work closely with business development team to understand future projects and resource needed• First line of clarification and explanation for customer related questions and support• Work with post silicon team for design intent and required validations
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPrinciple Digital Design Engineer (Logic)ID:59118
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustomer Service - Cantonese Speaker (Fresh Grads OK)ID:58923
3,700 MYR ~ 4,200 MYRPutrajaya/Cyberjaya, Other KL DistrictJob Description
- Provides an administrative support service to the Managed Services Client Service Desk team.- Provides entry level administrative tasks as required by the team.- Responsible for receiving, validating, and logging client requests, capturing the detail of the request.- Ensures the correct escalation procedure is followed on all critical calls and requests and assists with analyzing and interpreting the request to ensure the correct categorization and prioritization.- Works closely with colleagues to ensure the user is kept updated on the progress in relation to the resolution of the pending tickets / requests.- Ensures all relevant documents related to the tickets / requests are maintained, including the client’s information.- Communicates in a professional manner, provide updates and ensure clients are aware of the actions that are being undertaken on their behalf.- Performs any other related task as required.
Benefit
- Mobile Allowance RM200
- Annual Performance Individual Bonus
- Medical Benefit
- Dental Benefit
- Wellness Benefit
- Annual Leave
- Medical LeaveFront-end Web DeveloperID:58909
6,000 MYR ~ 12,000 MYRBangsarJob Description
Industry: IT, Website design, programming and develpmentRole: Frontend web development Special about this job: You will be in charge of web development using "RCMS" and "Kuroco", which is originally developed CRM system by Deverta. "RCMS" is specialized in simplify the contents management while another system "Kuroco" is specialized in API (Application programming Interface). We will continuously incorporate with the latest technology so you may also need to study & brush up your skills continuously to catch up with it.Also we require all engineers to be performing as a full stack engineer but not only front-end.Below is general job scope:-Develop new user-facing features-Build reusable code and libraries for future use-Ensure the technical feasibility of UI/UX designs-Optimize application for maximum speed and scalability-Assure that all user input is validated before submitting to back-end-Collaborate with other team members and stakeholders
Benefit
Salary; Depend on experience
-Transportation Allowance :RM 350 per month
-Medical Allowance(Claim basis) :RM200 per month (Max)
-Hospitalization (Claim basis) :RM5,000 per month (Max)
-Medical Examination / Special Consultation(Claim basis) :RM350 per month (Max)
-Annual Leave
A) For the first two years of your employment, entitled to 10 days annual leave.
B) At the start of your third (3rd) year serving the company, entitled to 14 days annual leave.
C) At the start of your fifth (5th) year serving the company, entitled to 18 days annual leave.
-Sick Leave: 14 days of paid sick leave a year, required to provide a medical certificate.
