26 Jobs: Manufacturing(Computer/Telecommunication)
Service Desk Shift Lead (Cantonese Speaker) (Working in Shift)ID:60897
4,930 MYR ~ 5,230 MYRPutrajaya/Cyberjaya, Other KL DistrictJob Description
JOB PURPOSE This role is responsible for leading the customer service helpdesk operations, providing high-quality service delivery in line with defined SLAs and business objectives. Serves as a key contact for customers from Hong Kong, coordinating with internal teams, carriers, vendors, and external parties to drive timely resolution of customer and service issues.KEY RESPONSIBILITIES- Responsible for customer service helpdesk operations, including receiving, validating, and logging client requests, capturing the detail of the request.- Ensures high-quality service delivery in line with defined SLAs and business objectives.- Coordinate closely with internal teams, carriers, vendors, and external parties to drive timely resolution of customer and service issues.- Ensures the correct escalation procedure is followed on all critical calls and requests and assists with analyzing and interpreting the request to ensure the correct categorization and prioritization.- Works closely with colleagues to ensure the user is kept updated on the progress in relation to the resolution of the pending tickets / requests.- Take ownership of complex, high-impact, or chronic fault cases, including customer communication and root-cause follow-up.- Lead or support customer complaint investigations, ensuring issues are properly analyzed, documented, and addressed.- Ensures all relevant documents related to the tickets / requests are maintained, including the client's information.- Identify operational gaps, recurring issues, and process inefficiencies, and recommend improvement actions to supervisors or management.- Communicates in a professional manner, provide updates and ensure clients are aware of the actions that are being undertaken on their behalf.- Provides an administrative support service to the Managed Services Client Service Desk team.- Participate in special projects, service onboarding activities, and process enhancement initiatives as assigned.
Benefit
- Phone Allowance: RM200
- Shift Allowance: RM230
- Annual Target Bonus (10% of Annual Basic Salary)
- Annual leave: 15 days
- Medical leave:14 days
- Insurance coverage:
- Outpatient: Reimbursement of outpatient medical expenses from panel hospitals/clinics (Employee & dependents)
- Group Hospital & Surgical Insurance (Hospitalisation, Surgical treatment and expenses): RM100,000 (Employee & dependents)
- Group Term Life Insurance: RM100,000 (Employee only)
- Group Personal Accident Insurance: RM150,000 (Employee only)
- Dental: RM750 per annum (reimbursable)
- Health Screening:
Reimbursable of annual health check-ups based on age limit
- Wellness: RM 550 per annum (reimbursable) for wellness benefits
- Wellness Leave: 2 days
- Volunteer Leave: 3 daysPMO Analyst (SAP Projects) (1 year contract)ID:60844
7,500 MYR ~ 8,500 MYRKota Damansara/Petaling JayaJob Description
■ JOB OVERVIEWThe PMO Analyst supports the planning, governance, reporting, and coordination activities of SAP and enterprise technology projects.The role works closely with Project Managers, Solution Architects, Functional Consultants, Technical Teams, Business Stakeholders, and System Integrators to ensure project information is accurate, timely, and aligned with PMO standards.This role is ideal for a candidate seeking to develop a career path toward Project Management or PMO Management.■ RESPONSIBILITIESProject Reporting & Governance- Prepare and maintain weekly and monthly project status reports.- Track project milestones, deliverables, and action items.- Consolidate project metrics and dashboards for management reporting.- Support governance meetings and follow up on agreed actions.- Ensure project documentation complies with PMO standards.Schedule & Action Tracking- Maintain project plans and milestone trackers.- Monitor completion of project activities and dependencies.- Follow up with team members on overdue actions and deliverables.- Support Project Managers with schedule updates and reporting.Risk & Issue Management- Maintain Risk, Issue, Assumption, and Dependency (RAID) logs.- Track risk mitigation and issue resolution activities.- Escalate overdue actions and unresolved issues to Project Managers.- Support preparation of risk and issue summaries for management reviews.Financial & Resource Support- Assist in tracking project budgets and purchase requests.- Support vendor timesheet and invoice tracking.- Maintain resource allocation and onboarding records.- Produce basic budget variance and resource utilization reports.SAP Project Coordination- Support SAP project activities across phases of delivery.- Coordinate workshops, project meetings, testing sessions, and cutover activities.- Track SAP deliverables and milestone completion.- Maintain project repositories and document libraries.Testing & Deployment Support- Monitor testing progress and defect status.- Consolidate SIT and UAT reporting metrics.- Track readiness activities for deployment and go-live.- Support preparation of project stage-gate materials.Stakeholder Coordination- Schedule project meetings and document meeting minutes.- Track decisions and action items.- Coordinate communications across business and IT stakeholders.- Support Project Managers in preparing executive presentations.
Benefit
・AL = <2Y 15d, 2~5Y 19d, >5Y 22d
・MC = <2Y 14d, 2~5 18d, >5Y 22d
・Mobile Allowance = RM 100
・Transport Allowance = RM 450
・All business travel claimable
・Outstation Allowance (amount based on location)
・Overseas Allowance (amount based on location
・Mileage = RM 0.70 / km (within Klang Valley travel)
・Medical Claim = RM 10,000 / year (including specialist)
・Flexi Plan up to RM 1,000 (Including dental, optical, and productivity gadgets)
・Insurance: Tokio Marine (PA, Hospitalization)
・Company Activities: Annual Dinner (by division), Sport Carnival (for all Panasonic group companies)
・Mobile Phone Allowance (Upon confirmation)
・Dental, Vision, Outpatient, Group Hospitalization, etc.Sales ExecutiveID:59346
5,000 MYR ~ 7,000 MYRShah AlamJob Description
- Develop and execute a strategic sales plan to secure, grow, and manage key corporate accounts.- Actively prospect and acquire new key accounts to expand market share in line with company growth objectives.- Build and maintain strong, long-term relationships with key decision-makers and influencers within client organizations.- Conduct in-depth business needs analysis to understand client challenges and position SHARP's MFP and Solutions offerings as critical to their digitization journey.- Prepare and deliver compelling, high-level presentations and proposals that articulate clear business benefits and ROI.- Collaborate effectively with internal technical, pre-sales, and support teams to design comprehensive solutions and ensure successful client outcomes.- Maintain a robust sales pipeline and provide accurate forecasting to the HOD.
Benefit
Salary: RM5,000 - 7,000
Working Hours: 8:30 AM – 5:30 PM (Mon–Fri)
Tools: Laptop provided.
Annual Leave: 12 days (less than 2 years), 15 days (2–5 years), 18 days (over 5 years). Yes.
Medical Leave: 30 days per year. For both of the position is 14 days (less than 2 years), 18 days (2–5 years), 22 days (over 5 years).
Insurance: Group PA
Allowances: Full reimbursement for toll, parking, and petrol for business use.Senior Mechanical Design EngineerID:60496
6,000 MYR ~ 7,500 MYRSimpang AmpatJob Description
<Competencies>• Develop systems that are reliable and effective by mitigating risk and reducing failure• Gather requirements, develop models and create prototypes in a timely and effective manner to increase a project’s safety and success• Identifies, formulate and solve engineering problems<Job Responsibilities / Percentage of Time> • Design and development of mechanical components from concept through production. (20%)• Take leadership of mechanical design in automation project. (20%) • Thorough design analysis and optimization of mechanical components including considerations of design for manufacturing and cost. (5%) • Plan and manage mechanical design schedule. (10%) • Conduct design reviews and provide design guidance to junior engineer. (10%) • Interface with customers and functional owners on mechanical design issue. (10%) • Responsible to complete design assembly drawings and details part drawings. (10%) • Checking of drawings and preparation of Bill of Materials (BOM). (5%) • Must prepare to travel local and overseas. (10%) • Be aware of the risks and opportunities related to the job assigned.• Be aware of the needs and expectation of interested party, the consequences of failure and their impact.
Benefit
Salary range: RM6,000 - RM7,000
Fixed allowances:
• Phone allowance
• Petrol allowance
AL: Start with 14 days
SL: 14 / 18 / 22 days
<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance
<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis
<If travelling>
• Daily allowance (Depending on the country they visit)Sales Engineer (Building Automation)ID:60281
3,500 MYR ~ 5,000 MYRSeputehJob Description
• Responsible for the sales & marketing of products, system and solution.• Response to all sales enquiries and prepare for the quotation and tender documents.• Responsible for meeting customer requirements through service deliveries, establishing customers and identifying potential business opportunities.• Develop and maintain good relationships with new and existing customers, end users, M&E consultants and contractors. • Responsible to meet yearly target to achieve KPI.• Timely report to superior for the sales activities. • Update customers on company’s new products regularly and obtain their feedback.• Prepare sales reports, presentation, proposal material and update job list.• Update and submit weekly report.• Responsible to follow up payment and collection with customers and update to Finance from time to time.• Ensure customer information to be kept confidentially and adequately according to company rules and regulations.• Work with engineering team to ensure after-sales service to customer, providing expert advice / consultancy, strengthening customer relationship, etc.• Work closely and maintain good communication within department and other departments. • Maintain compliance with all company policies and procedures.• Responsible for any other tasks assigned from time to time by superior.
Benefit
Salary range: RM3,500 - RM5,000
<Leaves>
• AL:14days/year
• ML:14days/year
<Allowances>
• Transportation: RM200/month
• Phone: RM200/month
<Misc.>
• Annual bonus (depending on company and individual performance)
• Free office parking
• Medical for dependents RM2,000/year
*Other benefits will be shared in more detail during interview sessionDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Technical EngineerID:60114
6,000 MYR ~ 7,000 MYRSimpang AmpatJob Description
• Machine assembly, standard part and fabrication part receiving, modifcation, alignment, test run, trouble shooting, installation and customer service as define by department Standard Operating Procedure (SOP), Work Instruction (WI) and Customer Specification. • Perform fine tuning, troubleshooting and analyze machine performance related issues followed by initiating rework or changes required.• Lead, support and coordinate with project team to resolve machine performance issues which is not able to solve by Production team within the allocated deadline/ budget/ quality for each project he is assigned including extra hours as needed. • Feedback and update on time to Production Manager/Mechanical Assembly Manager/Project Manager on project progress and issue encounters as define by Standard Operating Procedure (SOP) and Work Instruction (WI). • Records any information discovered during the fine tuning process that would make the process easier and more efficient; Production Improvement Activity. • Assist Production Manager/Mechanical Assembly Manager on section planning and lead improvement activities. • Develop training program and conduct training for production staffs including subcontractors. • Analyzes assembly blueprint and specification manual (for Build To Print) • Responsible for the use of production facilities and individual tools or equipment as define by Company Tools - Term and Condition. (5%) • Follows safety rules and keeps work area clean and organized as define by 5S Best Practice. • Performs other duties and assignments as instructed by superior from time to time.
Benefit
Salary range: RM6,000 - RM7,000
Fixed allowances:
• Phone allowance
• Petrol allowance
AL: Start with 14 days
SL: 14 / 18 / 22 days
<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance
<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis
<If travelling>
• Daily allowance (Depending on the country they visit)Memory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment