10 Jobs: Manufacturing(Computer/Telecommunication)
Customer Service - Cantonese Speaker (Fresh Grads OK)ID:58923
3,700 MYR ~ 4,200 MYRPutrajaya/Cyberjaya, Other KL DistrictJob Description
- Provides an administrative support service to the Managed Services Client Service Desk team.- Provides entry level administrative tasks as required by the team.- Responsible for receiving, validating, and logging client requests, capturing the detail of the request.- Ensures the correct escalation procedure is followed on all critical calls and requests and assists with analyzing and interpreting the request to ensure the correct categorization and prioritization.- Works closely with colleagues to ensure the user is kept updated on the progress in relation to the resolution of the pending tickets / requests.- Ensures all relevant documents related to the tickets / requests are maintained, including the client’s information.- Communicates in a professional manner, provide updates and ensure clients are aware of the actions that are being undertaken on their behalf.- Performs any other related task as required.
Benefit
- Mobile Allowance RM200
- Annual Performance Individual Bonus
- Medical Benefit
- Dental Benefit
- Wellness Benefit
- Annual Leave
- Medical LeaveFront-end Web DeveloperID:58909
6,000 MYR ~ 12,000 MYRBangsarJob Description
Industry: IT, Website design, programming and develpmentRole: Frontend web development Special about this job: You will be in charge of web development using "RCMS" and "Kuroco", which is originally developed CRM system by Deverta. "RCMS" is specialized in simplify the contents management while another system "Kuroco" is specialized in API (Application programming Interface). We will continuously incorporate with the latest technology so you may also need to study & brush up your skills continuously to catch up with it.Also we require all engineers to be performing as a full stack engineer but not only front-end.Below is general job scope:-Develop new user-facing features-Build reusable code and libraries for future use-Ensure the technical feasibility of UI/UX designs-Optimize application for maximum speed and scalability-Assure that all user input is validated before submitting to back-end-Collaborate with other team members and stakeholders
Benefit
Salary; Depend on experience
-Transportation Allowance :RM 350 per month
-Medical Allowance(Claim basis) :RM200 per month (Max)
-Hospitalization (Claim basis) :RM5,000 per month (Max)
-Medical Examination / Special Consultation(Claim basis) :RM350 per month (Max)
-Annual Leave
A) For the first two years of your employment, entitled to 10 days annual leave.
B) At the start of your third (3rd) year serving the company, entitled to 14 days annual leave.
C) At the start of your fifth (5th) year serving the company, entitled to 18 days annual leave.
-Sick Leave: 14 days of paid sick leave a year, required to provide a medical certificate.Account ManagerID:54452
11,500 MYR ~ 17,000 MYRCheras (KL)Job Description
- Check if the bookkeeping and ledgers are accurate- Check daily transaction , Pretty cash timely. - Collaborate with an accounting firm for financial statement preparation- Prepare financial statements such as income statements, balance sheets, and cash flow statements for presentation to management and shareholders.- Prepare and submit tax returns, calculate taxes accurately- Supprot to create financial plans for the future by forecasting income and expenses.- Audit internal financial processes and transactions to prevent fraud.- Coordinate with external auditing firms to report accounting .- Calculating and Reviewing provision- Reporting to Senior Manager of Accounting Department
Benefit
- EPF(11%), SOCSO provided
- Bonus(Depends on the Performance - 2months in 2024)
- Transportation Allowance(Maximum RM200)
LRT/MRT = public total fare
Motorcycle = RM0.45/km
Car = RM0.70/km
AL:
14 days (0 to 1 year),
16 days (1 to 4 year)
18 days (After 4 year)
MC:
14 days (0 to 2 year)
16 days (3 to 4 year)
18 days (After 4 years)
Medical Claims: RM1,000 per year
Insurance :
AXA Affin (Group Hospitalization & Personal Accident)
Others :
- Annual Medical Checkup (Leader and Above)
- Annual Medical Checkup (Staff work more than 1 year and aged above 30 years)
- Housing Allowance
- Education Benefits
- Medical Life and Accident Insurance for all staff
- Position Allowance (Instructor and Leader)
- Birth Allowance
- Marriage Allowance
- Loyalty Award
- Cleaning and Good Attendance Award
- Team Entertainment Allowance
- Bereavement Allowance
- Field Visit Allowance
- Accommodation Allowance (for Visit)Senior System Board Design EngineerID:58749
10,000 MYR ~ 40,000 MYRBayan LepasJob Description
• Lead the end-to-end development of complex multilayer system boards, including architecture definition, schematic design & technical decision-making.• Drive component selection, trade-off analysis & architecture optimization to meet electrical, thermal, and mechanical constraints.• Ensure high-speed signal integrity, power integrity & EMI/EMC compliance through simulation, design & testing.• Lead board bring-up, root cause analysis, and system-level debug using lab instruments (oscilloscopes, logic analyzers, spectrum analyzers, etc.).• Define test strategies and validate hardware against functional, environmental, and reliability requirements.• Prepare and review detailed design documentation: schematics, BOMs, layout constraints, test reports, and manufacturing files.• Collaborate with PCB layout engineers on components placements, routing and PCB stack up.• Skilful on handing rework tool to preforming board rework and modifications to hardware components.• Collaborate with cross-functional teams including SoC, firmware, packaging, mechanical, and manufacturing teams.• Interface with suppliers, PCB fabrication and assembly vendors for prototyping and production.• Provide technical leadership, mentoring, and code/design reviews for junior team members.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design / MicroarchitectID:58605
15,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to drive a low power and complex design to completions.2. IP Quality Responsibility• Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.3. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design / MicroarchitectID:58607
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Logic Design Principle EngineerID:58602
20,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The IP Logic Design Principle Engineer will be responsible for architecting microarchitecture design implementation of an IP, spanning across all IP stack such as application layer, transaction layer, link layer, die to die layer, physical layer. Ability to code verilog / system verilog RTL for complex IP, review RTL coding, orchestra IP development phase for projects from beginning to completion. This includes the ability to technically drive the IP team on Design / Validation in completing technical tasks up to IP releases for customers. Candidate must be also capable of solving high speed timing convergence on various processes and collaborate with cross-functional teams to meet project specifications. The role will drive performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Microarchitecture Definitions• Define microarchitecture definition across layers and define a clean inter unit partition requirements.• Drive design team to deliver best-in-class IP design that optimizes for area, latency, power and performance.• Ability to distribute and drive the design team to implement high quality design and meeting time to market requirements.2. IP Design Responsibility• Implement very complicated high-speed design which can converge timing convergence at high frequency.• Capable of orchestrating the team on right directions of timing convergence, CDC, lintra and etc. for tools closure.3. IP Quality Responsibility• Review IP design and validation testplan to make sure IP Design is at top notch quality.4. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan BaruJob Description
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNetwork-on-Chip (NoC) Team Engineering DirectorID:58599
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan BaruJob Description
This role will lead the architecture, design, and development of high-performance interconnect solutions for SoCs, chiplets, and advanced packaging systems. The ideal candidate will have deep expertise in NoC architecture, RTL/micro-architecture design, performance modeling, and verification, combined with strong leadership skills. Experience in both hardware and software development is a strong plus, as it enables system-level optimization, modeling, and seamless HW/SW co-design for next-generation NoC solutions. The NoC Team Director will drive technical strategy, manage execution, mentor a multidisciplinary team, and collaborate with cross-functional partners to deliver state-of-the-art interconnect IP for data-intensive and AI-driven applications. Key Responsibilities1. Leadership & Strategy• Define and execute the company’s NoC technology roadmap, aligned with product and system- level requirements.• Build, mentor, and lead a high-performing team of architects, designers, verification engineers, and performance modelers.• Foster innovation in NoC design, methodology, and automation to achieve best-in-class power, performance, and area (PPA).2. NoC Architecture & Design• Lead the design of scalable, configurable, and high-bandwidth NoC architectures for heterogeneous SoCs and multi-die systems.• Drive micro-architecture, RTL design, and integration of NoC subsystems, including coherency, QoS, and security features.• Oversee performance modeling, traffic analysis, and system-level simulation to ensure NoC meets latency and bandwidth requirements.• Collaborate with physical design teams to optimize NoC topology, floorplanning, and timing closure. 3. Cross-Functional Collaboration• Partner with CPU/GPU/AI accelerator, memory subsystem, and IP teams to define NoC interfaces and integration requirements.• Collaborate with software teams on NoC modeling frameworks, traffic generators, drivers, and firmware for validation and optimization.• Engage with product and system architects to align NoC capabilities with end-market requirements (AI/ML, datacenter, automotive, mobile).4. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Layout and Physical Design EngineerID:58373
6,000 MYR ~ 15,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking analog/mixed-signal IP layout and physical design to lead layout implementation, RTL-to-GDSII execution and mentor juniors while working with top EDA tools. Be part of a team building high-performance semiconductor solutions. Job Description:• Independently execute layout of analog/mixed-signal IP blocks (e.g., ADCs, LDOs, PLLs, bandgaps, IOs)• Work closely with logic and circuit designers to meet performance, area, and matching constraints• Support top-level floorplanning and layout integration• Perform DRC/LVS/PEX and support sign-off processes• Participate in technical reviews and contribute to best practices in layout & physical design methodology• Block execution of physical design, including synthesis, Place and Route and Design and Timing Closure• Lead and guide junior engineers on the block execution
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
