42 Jobs: Manufacturing(Computer/Telecommunication)
Sales Engineer (Building Automation)ID:60281
3,500 MYR ~ 5,000 MYRSeputehJob Description
• Responsible for the sales & marketing of products, system and solution.• Response to all sales enquiries and prepare for the quotation and tender documents.• Responsible for meeting customer requirements through service deliveries, establishing customers and identifying potential business opportunities.• Develop and maintain good relationships with new and existing customers, end users, M&E consultants and contractors. • Responsible to meet yearly target to achieve KPI.• Timely report to superior for the sales activities. • Update customers on company’s new products regularly and obtain their feedback.• Prepare sales reports, presentation, proposal material and update job list.• Update and submit weekly report.• Responsible to follow up payment and collection with customers and update to Finance from time to time.• Ensure customer information to be kept confidentially and adequately according to company rules and regulations.• Work with engineering team to ensure after-sales service to customer, providing expert advice / consultancy, strengthening customer relationship, etc.• Work closely and maintain good communication within department and other departments. • Maintain compliance with all company policies and procedures.• Responsible for any other tasks assigned from time to time by superior.
Benefit
Salary range: RM3,500 - RM5,000
<Leaves>
• AL:14days/year
• ML:14days/year
<Allowances>
• Transportation: RM200/month
• Phone: RM200/month
<Misc.>
• Annual bonus (depending on company and individual performance)
• Free office parking
• Medical for dependents RM2,000/year
*Other benefits will be shared in more detail during interview sessionSenior/Staff Design for Testability (DFT) EngineerID:60263
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced and strategic Senior or Staff DFT Design Engineer to join our team and in support the company’s ASIC design and IP development initiatives in the area of Design for Testability (DFT) design and verification. The candidate will play a key role in leading the planning and execution of various DFT features implementation and verification.Key Responsibilities:• DFT microarchitecture planning, DFT rtl generation/integration and verification of various DFT feature.• Memory BIST design implementation and verification for IP and ASIC projects.o Mbist logic insertion, integration and verification.o Mbist collateral generations including mbist pattern and timing constraint.• Scan design implementation and verification for IP and custom ASIC.o Scan controller generation (clock/reset control, test compression) implementation and scan chain stitchingo ATPG pattern generations and GLS simulation to verify the scan design.o Scan collaterals generation including scan constraint, scan timing closure, ATPG pattern debug etc.• JTAG/Boundary Scan design implementation and verificationo Tap controller design and verificationo Boundary scan chain implementation at IP and soc level, bscan verification and bsdl generation.• Post silicon debug and test pattern bring up supports to enable silicon power on activities and high-volume manufacturing testing.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Mechanical Design EngineerID:60118
6,000 MYR ~ 7,500 MYRSimpang AmpatJob Description
<Competencies>• Develop systems that are reliable and effective by mitigating risk and reducing failure• Gather requirements, develop models and create prototypes in a timely and effective manner to increase a project’s safety and success• Identifies, formulate and solve engineering problems<Job Responsibilities / Percentage of Time> • Design and development of mechanical components from concept through production. • Take leadership of mechanical design in automation project. • Thorough design analysis and optimization of mechanical components including considerations of design for manufacturing and cost. • Plan and manage mechanical design schedule. • Conduct design reviews and provide design guidance to junior engineer. • Interface with customers and functional owners on mechanical design issue. • Responsible to complete design assembly drawings and details part drawings. • Checking of drawings and preparation of Bill of Materials (BOM). • Must prepare to travel local and overseas. • Be aware of the risks and opportunities related to the job assigned.• Be aware of the needs and expectation of interested party, the consequences of failure and their impact.
Benefit
Salary range: RM6,000 - RM7,000
Fixed allowances:
• Phone allowance
• Petrol allowance
AL: Start with 14 days
SL: 14 / 18 / 22 days
<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance
<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis
<If travelling>
• Daily allowance (Depending on the country they visit)Physical Design Lead EngineerID:60207
10,000 MYR ~ 18,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementChief Financial Officer (CFO)ID:59799
15,000 MYR ~ 25,000 MYRCheras (KL)Job Description
■Accounting & Financial Governance- Ensure integrity and accuracy of all financial records, accounting policies, and group-wide financial reporting- Oversee monthly, quarterly, and annual closing processes, ensuring timely and compliant financial statements- Lead the preparation of consolidated financial statements in collaboration with external accounting firms and auditors- Review and approve financial reports, including income statements, balance sheets, and cash flow statements for board and shareholder reporting- Ensure full compliance with applicable tax regulations, including corporate income tax, withholding tax, and indirect taxes (e.g., SST/GST where applicable)- Oversee tax reporting, filings, and audit processes, ensuring accuracy and regulatory compliance across jurisdictions- Strengthen internal controls, risk management frameworks, and governance structures to prevent fraud and ensure financial integrity- Act as the final escalation point for accounting matters and reporting to the Board of Directors■Corporate Finance & Strategic Financial Management- Lead corporate financial strategy, including long-term value creation, capital allocation, and financial sustainability planningConduct ROI evaluation and financial feasibility analysis for strategic initiatives, investments, and expansion projects- Develop and own 3–5 year financial forecasts, group-level budgeting, and strategic financial planning- Lead capital raising activities, including debt financing, equity fundraising, and structured financing to support business growth- Manage relationships with key financial stakeholders, including investors, banks, private equity, and venture capital firms- Oversee investor relations, including communication, reporting, and management of data rooms and due diligence processes- Lead negotiation of financing terms, credit facilities, covenants, and investment structures- Optimize group structure and capital structure to improve tax efficiency, profitability, and IPO readiness- Provide strategic oversight on mergers and acquisitions, joint ventures, and market expansion opportunities- Advise the CEO and Board on financial strategy, investment decisions, risk exposure, and corporate transformation initiatives- Monitor business performance metrics, including ROI and IRR, ensuring alignment with long-term strategic objectives- Drive financial digital transformation initiatives, including ERP implementation and data-driven financial planning systems
Benefit
- EPF(11%), SOCSO provided
- Bonus(Depends on the Performance - 2months in 2024)
- Transportation Allowance(Maximum RM200)
LRT/MRT = public total fare
Motorcycle = RM0.45/km
Car = RM0.70/km
AL:
14 days (0 to 1 year),
16 days (1 to 4 year)
18 days (After 4 year)
MC:
14 days (0 to 2 year)
16 days (3 to 4 year)
18 days (After 4 years)
Medical Claims: RM1,000 per year
Insurance :
AXA Affin (Group Hospitalization & Personal Accident)
Others :
- Annual Medical Checkup (Leader and Above)
- Annual Medical Checkup (Staff work more than 1 year and aged above 30 years)
- Housing Allowance
- Education Benefits
- Medical Life and Accident Insurance for all staff
- Position Allowance (Instructor and Leader)
- Birth Allowance
- Marriage Allowance
- Loyalty Award
- Cleaning and Good Attendance Award
- Team Entertainment Allowance
- Bereavement Allowance
- Field Visit Allowance
- Accommodation Allowance (for Visit)Logic Design EngineerID:60086
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Logic Design Engineer to implement RTL design. Familiarity with LPDDR and HBM memory interface IP will be a plus. The engineer will own block-level microarchitecture, RTL coding, and design sign-off from specification through customer delivery. Seniority level to be determined by experience.Key Responsibilities• Define and implement block-level and layer-level RTL for various IPs, meeting high-frequency timing requirements at advanced process nodes.• Drive microarchitecture definition for assigned blocks in collaboration with senior architects; document design decisions and trade-offs clearly for cross-functional review.• Achieve timing closure at high frequencies; work with physical design and STA teams to resolve setup/hold violations, manage clock domain crossings (CDC), and support floorplan iterations.• Execute design quality checks: CDC analysis, lint (Lintra), formal equivalence verification (FEV), and low-power (UPF) flows; resolve violations to achieve clean convergence.• Produce and review test plans for block-level functional verification, including black-box and white-box simulation, FPV, and emulation; collaborate with DV engineers to resolve design bugs.• Own IP release deliverables for customer handoff: RTL packages, netlists, and accompanying documentation; ensure release quality and compliance with customer specification.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementHead of Department (Accounting)ID:59493
11,500 MYR ~ 17,000 MYRCheras (KL)Job Description
・Check if the bookkeeping and ledgers are accurate・Check daily transaction, pretty cash timely.・Collaborate with an accounting firm for financial statement preparation・Prepare financial statements such as income statements, balance sheets, and cash flow statements for presentation to management and shareholders.・Prepare and submit tax returns, calculate taxes accurately・Support to create financial plans for the future by forecasting income and expenses.・Audit internal financial processes and transactions to prevent fraud.・Coordinate with external auditing firms to report accounting.・Reporting to Director
Benefit
- EPF(11%), SOCSO provided
- Bonus(Depends on the Performance - 2months in 2024)
- Transportation Allowance(Maximum RM200)
LRT/MRT = public total fare
Motorcycle = RM0.45/km
Car = RM0.70/km
AL:
14 days (0 to 1 year),
16 days (1 to 4 year)
18 days (After 4 year)
MC:
14 days (0 to 2 year)
16 days (3 to 4 year)
18 days (After 4 years)
Medical Claims: RM1,000 per year
Insurance :
AXA Affin (Group Hospitalization & Personal Accident)
Others :
- Annual Medical Checkup (Leader and Above)
- Annual Medical Checkup (Staff work more than 1 year and aged above 30 years)
- Housing Allowance
- Education Benefits
- Medical Life and Accident Insurance for all staff
- Position Allowance (Instructor and Leader)
- Birth Allowance
- Marriage Allowance
- Loyalty Award
- Cleaning and Good Attendance Award
- Team Entertainment Allowance
- Bereavement Allowance
- Field Visit Allowance
- Accommodation Allowance (for Visit)Senior Technical EngineerID:60114
6,000 MYR ~ 7,000 MYRSimpang AmpatJob Description
• Machine assembly, standard part and fabrication part receiving, modifcation, alignment, test run, trouble shooting, installation and customer service as define by department Standard Operating Procedure (SOP), Work Instruction (WI) and Customer Specification. • Perform fine tuning, troubleshooting and analyze machine performance related issues followed by initiating rework or changes required.• Lead, support and coordinate with project team to resolve machine performance issues which is not able to solve by Production team within the allocated deadline/ budget/ quality for each project he is assigned including extra hours as needed. • Feedback and update on time to Production Manager/Mechanical Assembly Manager/Project Manager on project progress and issue encounters as define by Standard Operating Procedure (SOP) and Work Instruction (WI). • Records any information discovered during the fine tuning process that would make the process easier and more efficient; Production Improvement Activity. • Assist Production Manager/Mechanical Assembly Manager on section planning and lead improvement activities. • Develop training program and conduct training for production staffs including subcontractors. • Analyzes assembly blueprint and specification manual (for Build To Print) • Responsible for the use of production facilities and individual tools or equipment as define by Company Tools - Term and Condition. (5%) • Follows safety rules and keeps work area clean and organized as define by 5S Best Practice. • Performs other duties and assignments as instructed by superior from time to time.
Benefit
Salary range: RM6,000 - RM7,000
Fixed allowances:
• Phone allowance
• Petrol allowance
AL: Start with 14 days
SL: 14 / 18 / 22 days
<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance
<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis
<If travelling>
• Daily allowance (Depending on the country they visit)Logic Design Verification EngineerID:60088
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking to hire Logic Verification Engineer. Familiarity with LPDDR and HBM memory interface IP will be a plus. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain UVM-based verification environments for various IPs, including constrained-random testbenches, protocol-aware monitors, scoreboards, and checkers.• Author detailed verification plans based on specifications, architectural documents, and use-case scenarios; own coverage closure end-to-end.• Drive coverage-driven verification (CDV): functional coverage (covergroups/coverpoints), code coverage (statement, branch, toggle), and SystemVerilog assertions (SVA); identify gaps and close with targeted test scenarios.• Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis; apply Formal Property Verification (FPV) to prove critical design properties.• Debug simulation failures in collaboration with RTL designers; document results, coverage metrics, and regression summaries for traceability and sign-off.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementDFT Logic Design EngineerID:60087
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a DFT Logic Design Engineer to implement testability infrastructure across our digital IP portfolio. You will define DFT strategy, integrate scan and BIST structures at the RTL level, and drive fault coverage from early design through silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Define and own the DFT architecture for digital and mixed-signal blocks: scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, and MBIST/LBIST planning; document and maintain the DFT specification throughout the design cycle.• Develop and integrate DFT RTL (SystemVerilog/Verilog): scan wrappers, BIST controllers, test access ports, and clock/reset control logic; ensure DFT structures are synthesis-clean, timing-closed, and do not degrade functional performance or power.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets; achieve and sign off on target fault coverage metrics agreed with the test engineering team.• Collaborate with RTL designers on DFT-aware coding guidelines; perform DFT rule checking, CDC analysis, and Lint to identify and resolve testability violations early in the design cycle before netlist handoff.• Support physical design handoff: provide scan chain ordering recommendations, validate DFT netlist post-layout (LEC, STA), and resolve DFT-related ECOs during timing closure and tapeout.• Support post-silicon validation and ATE bring-up: work with test engineers to load and debug ATPG patterns on ATE platforms, analyze yield data, and triage failing patterns back to root-cause RTL or physical design issues.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
