27 Jobs: Manufacturing(Computer/Telecommunication)
Memory IP Architect / SoC uArchitectID:61253
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Role OverviewWe are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.Key Responsibilities• NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.• Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.• Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.• Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.• Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.• Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.• Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory IP Architect / SoC uArchitectID:61252
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
We are looking for an experienced Memory IP Architect / uArchitect to lead the architecture and development of next-generation memory solutions for AI, HPC, networking, and custom ASIC applications.This role will drive the definition of memory subsystems, memory controllers, and high-performance SoC memory solutions from concept through silicon.Responsibilities• Define architecture and specifications for Memory IP and SoC subsystems.• Lead memory architecture for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache subsystems.• Drive architecture trade-offs across performance, power, area, and cost.• Develop performance models and conduct architecture exploration.• Define memory hierarchy, and system-level optimization strategies.• Collaborate with RTL, DV, DFT, PD, Packaging, Firmware, and Software teams.• Support customer engagements, technical reviews, and roadmap planning.• Guide implementation through silicon bring-up and performance tuning.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementRTL Design Engineer (Junior/Senior)ID:61251
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Position OverviewWe are seeking RTL Design Engineers at Junior/Intermediate and Senior levels to join our Hardware Engineering team, focusing on ASIC and SoC design.The successful candidates will be responsible for RTL development, functional verification, simulation, debugging and design quality throughout the front-end design flow. Depending on experience and seniority, the role will involve implementing well-defined RTL blocks under guidance or independently owning RTL blocks from specification through verification closure and sign-off.Key ResponsibilitiesA. RTL Design & Development- Develop synthesizable RTL using Verilog and/or SystemVerilog in accordance with design specifications and team coding guidelines.- Implement and maintain RTL blocks for ASIC and SoC designs, ensuring functionality, code quality and design efficiency.- Apply synchronous design principles, including clocking, reset strategies, data valid/ready handshaking and clock domain crossing (CDC) techniques.- Design and maintain functional blocks such as finite state machines (FSMs), FIFOs, arbiters, register files, control logic and data paths.- Work with standard bus protocols, including APB and AHB-Lite, with awareness of AXI4.- Consider area, power and performance (PPA) implications when developing and optimizing RTL.- Collaborate with design, verification, physical design (PD), DFT and other cross-functional teams to resolve design issues and improve implementation quality.Junior / Intermediate Level- Implement well-defined RTL blocks based on detailed microarchitecture specifications under the guidance of senior engineers or technical leads.- Develop foundational knowledge of RTL design methodologies, synthesis implications, CDC concepts and low-power design techniques.- Participate in design reviews, identify potential corner cases and proactively raise technical questions or design concerns.- Improve RTL quality and design efficiency based on code review feedback.Senior Level- Independently own RTL blocks from specification review and design implementation through verification closure and sign-off.- Contribute to microarchitecture definition, design specification documentation and technical design reviews.- Optimize RTL for timing closure, area and power through techniques such as pipelining, retiming and appropriate coding strategies.- Implement and evaluate low-power design techniques, including clock gating, isolation cells and retention flops.- Resolve complex RTL design issues and work with physical design teams to address timing and place-and-route feedback.- Provide technical guidance and informal mentoring to junior engineers.B. Functional Verification & Simulation- Develop and execute directed and self-checking SystemVerilog testbenches to verify RTL functionality.- Run simulations, debug functional failures and analyze waveforms using industry-standard tools.- Write SystemVerilog Assertions (SVA) to capture design intent and verify key interface requirements.- Apply functional coverage concepts to assess verification completeness and identify potential coverage gaps.- Collaborate with design verification engineers to investigate issues and ensure design quality.Junior / Intermediate Level- Develop directed testbenches for assigned RTL blocks and execute simulations using tools such as Synopsys VCS, Questa or Icarus Verilog.- Perform waveform debugging using Verdi, DVE or equivalent tools.- Demonstrate basic understanding of UVM concepts, including agents, sequences and scoreboards.- Add basic functional coverage points and develop familiarity with assertions and verification methodologies.Senior Level- Develop and debug more comprehensive testbenches and contribute to UVM agents, sequences and verification environments.- Interpret coverage reports and drive functional coverage closure in collaboration with verification teams.- Apply assertions, assumptions and cover properties, with exposure to formal verification methodologies.- Investigate complex simulation failures and contribute to root-cause analysis across RTL, verification and integration issues.C. Design Quality, Sign-Off & Integration- Ensure RTL designs comply with applicable design specifications, coding standards and quality requirements.- Review simulation results, lint reports and timing information to identify and resolve potential design issues.- Understand the impact of RTL changes on synthesis, timing, integration and downstream implementation.- Collaborate with verification, DFT and physical design teams throughout the design lifecycle.Junior / Intermediate Level- Develop an understanding of static timing analysis (STA), including setup and hold violations.- Resolve common lint warnings and develop familiarity with CDC analysis and synchronizer insertion.- Understand basic DFT concepts, including scan chains and test modes.- Support design reviews and sign-off activities under senior engineer guidance.Senior Level- Interpret STA reports, timing slack and critical paths, and implement RTL changes to address timing issues.- Resolve common CDC and reset domain crossing (RDC) violations and lint issues.- Apply DFT awareness when designing RTL and supporting scan insertion and test mode requirements.- Work closely with physical design teams to resolve implementation-related issues and support design sign-off.- Take ownership of RTL quality and verification closure for assigned blocks.D. Scripting, Automation & Design Tools- Use scripting languages and automation tools to improve design, simulation and debugging efficiency.- Work with existing simulation flows, tool scripts, file lists and build configurations.- Analyze simulation logs and support the maintenance of design and verification workflows.Junior / Intermediate Level- Write basic Python, Tcl or shell scripts to automate repetitive simulation tasks.- Edit existing Makefiles and Tcl run scripts and parse simulation logs.- Demonstrate proficiency in at least one industry-standard simulation tool.Senior Level- Develop and maintain Python, Tcl or shell scripts for simulation automation, regression execution and log analysis.- Manage file lists, hierarchy extraction and simulation flow configurations.- Troubleshoot tool-flow issues and improve automation efficiency where appropriate.- Utilize synthesis and formal verification tools as required by the project.E. Technical Collaboration & Continuous Improvement- Collaborate with cross-functional engineering teams to support successful ASIC/SoC design implementation.- Participate in design reviews, technical discussions and knowledge-sharing activities.- Maintain clear design documentation and communicate technical issues, progress and blockers effectively.- Continuously improve technical knowledge of RTL design, verification methodologies and EDA tools.Junior / Intermediate Level- Work collaboratively within an established design team, seek clarification when requirements are unclear and incorporate feedback from senior engineers.- Provide timely progress updates and proactively communicate design issues or blockers.Senior Level- Drive technical discussions for assigned RTL blocks and document design decisions and implementation considerations.- Coordinate closely with design verification, DFT, physical design and software teams to resolve technical issues.- Mentor junior engineers and contribute to improving team design practices.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Mechanical Design EngineerID:60496
6,000 MYR ~ 7,500 MYRSimpang AmpatJob Description
<Competencies>• Develop systems that are reliable and effective by mitigating risk and reducing failure• Gather requirements, develop models and create prototypes in a timely and effective manner to increase a project’s safety and success• Identifies, formulate and solve engineering problems<Job Responsibilities / Percentage of Time> • Design and development of mechanical components from concept through production. (20%)• Take leadership of mechanical design in automation project. (20%) • Thorough design analysis and optimization of mechanical components including considerations of design for manufacturing and cost. (5%) • Plan and manage mechanical design schedule. (10%) • Conduct design reviews and provide design guidance to junior engineer. (10%) • Interface with customers and functional owners on mechanical design issue. (10%) • Responsible to complete design assembly drawings and details part drawings. (10%) • Checking of drawings and preparation of Bill of Materials (BOM). (5%) • Must prepare to travel local and overseas. (10%) • Be aware of the risks and opportunities related to the job assigned.• Be aware of the needs and expectation of interested party, the consequences of failure and their impact.
Benefit
Salary range: RM6,000 - RM7,000
Fixed allowances:
• Phone allowance
• Petrol allowance
AL: Start with 14 days
SL: 14 / 18 / 22 days
<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance
<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis
<If travelling>
• Daily allowance (Depending on the country they visit)Emulation and Prototyping Engineer (Senior/Lead)ID:61003
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced Emulation & Prototyping Manager to lead the emulation team supporting IP, SoC, and system-level development programs. The role is responsible for defining emulation strategies, managing project execution, developing engineering talent, and driving successful pre-silicon validation and software enablement using industry-leading emulation and prototyping platforms.Key Responsibilities1. Team & People Leadership• Lead, mentor, and grow a high-performing emulation/prototyping team.• Manage resource planning, staffing, performance management, and career development.• Establish engineering best practices, methodologies, and continuous improvement initiatives.2. Technical Leadership• Define and drive emulation/prototyping strategies for IP and SoC programs.• Provide technical guidance on platform architecture, RTL partitioning, acceleration methodologies, and debug.• Evaluate and deploy industry-leading emulation/prototyping technologies and infrastructure.3. Project Delivery• Drive execution of multiple emulation projects to meet quality, schedule, and budget objectives.• Manage project planning, effort estimation, risk assessment, and resource allocation.• Track project progress and provide regular status updates to management and stakeholders.4. Cross-Functional Collaboration• Partner with architects, RTL, DV, firmware, and software teams to enable pre-silicon validation and software bring-up.• Work closely with customers, partners, and EDA vendors to support project and business objectives.• Promote reuse, automation, and standardization across engineering teams.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementService Desk Shift Lead (Cantonese Speaker) (Working in Shift)ID:60897
4,930 MYR ~ 5,230 MYRPutrajaya/Cyberjaya, Other KL DistrictJob Description
JOB PURPOSE This role is responsible for leading the customer service helpdesk operations, providing high-quality service delivery in line with defined SLAs and business objectives. Serves as a key contact for customers from Hong Kong, coordinating with internal teams, carriers, vendors, and external parties to drive timely resolution of customer and service issues.KEY RESPONSIBILITIES- Responsible for customer service helpdesk operations, including receiving, validating, and logging client requests, capturing the detail of the request.- Ensures high-quality service delivery in line with defined SLAs and business objectives.- Coordinate closely with internal teams, carriers, vendors, and external parties to drive timely resolution of customer and service issues.- Ensures the correct escalation procedure is followed on all critical calls and requests and assists with analyzing and interpreting the request to ensure the correct categorization and prioritization.- Works closely with colleagues to ensure the user is kept updated on the progress in relation to the resolution of the pending tickets / requests.- Take ownership of complex, high-impact, or chronic fault cases, including customer communication and root-cause follow-up.- Lead or support customer complaint investigations, ensuring issues are properly analyzed, documented, and addressed.- Ensures all relevant documents related to the tickets / requests are maintained, including the client's information.- Identify operational gaps, recurring issues, and process inefficiencies, and recommend improvement actions to supervisors or management.- Communicates in a professional manner, provide updates and ensure clients are aware of the actions that are being undertaken on their behalf.- Provides an administrative support service to the Managed Services Client Service Desk team.- Participate in special projects, service onboarding activities, and process enhancement initiatives as assigned.
Benefit
- Phone Allowance: RM200
- Shift Allowance: RM230
- Annual Target Bonus (10% of Annual Basic Salary)
- Annual leave: 15 days
- Medical leave:14 days
- Insurance coverage:
- Outpatient: Reimbursement of outpatient medical expenses from panel hospitals/clinics (Employee & dependents)
- Group Hospital & Surgical Insurance (Hospitalisation, Surgical treatment and expenses): RM100,000 (Employee & dependents)
- Group Term Life Insurance: RM100,000 (Employee only)
- Group Personal Accident Insurance: RM150,000 (Employee only)
- Dental: RM750 per annum (reimbursable)
- Health Screening:
Reimbursable of annual health check-ups based on age limit
- Wellness: RM 550 per annum (reimbursable) for wellness benefits
- Wellness Leave: 2 days
- Volunteer Leave: 3 daysSales ExecutiveID:59346
5,000 MYR ~ 7,000 MYRShah AlamJob Description
- Develop and execute a strategic sales plan to secure, grow, and manage key corporate accounts.- Actively prospect and acquire new key accounts to expand market share in line with company growth objectives.- Build and maintain strong, long-term relationships with key decision-makers and influencers within client organizations.- Conduct in-depth business needs analysis to understand client challenges and position SHARP's MFP and Solutions offerings as critical to their digitization journey.- Prepare and deliver compelling, high-level presentations and proposals that articulate clear business benefits and ROI.- Collaborate effectively with internal technical, pre-sales, and support teams to design comprehensive solutions and ensure successful client outcomes.- Maintain a robust sales pipeline and provide accurate forecasting to the HOD.
Benefit
Salary: RM5,000 - 7,000
Working Hours: 8:30 AM – 5:30 PM (Mon–Fri)
Tools: Laptop provided.
Annual Leave: 12 days (less than 2 years), 15 days (2–5 years), 18 days (over 5 years). Yes.
Medical Leave: 30 days per year. For both of the position is 14 days (less than 2 years), 18 days (2–5 years), 22 days (over 5 years).
Insurance: Group PA
Allowances: Full reimbursement for toll, parking, and petrol for business use.Sales Engineer (Building Automation)ID:60281
3,500 MYR ~ 5,000 MYRSeputehJob Description
• Responsible for the sales & marketing of products, system and solution.• Response to all sales enquiries and prepare for the quotation and tender documents.• Responsible for meeting customer requirements through service deliveries, establishing customers and identifying potential business opportunities.• Develop and maintain good relationships with new and existing customers, end users, M&E consultants and contractors. • Responsible to meet yearly target to achieve KPI.• Timely report to superior for the sales activities. • Update customers on company’s new products regularly and obtain their feedback.• Prepare sales reports, presentation, proposal material and update job list.• Update and submit weekly report.• Responsible to follow up payment and collection with customers and update to Finance from time to time.• Ensure customer information to be kept confidentially and adequately according to company rules and regulations.• Work with engineering team to ensure after-sales service to customer, providing expert advice / consultancy, strengthening customer relationship, etc.• Work closely and maintain good communication within department and other departments. • Maintain compliance with all company policies and procedures.• Responsible for any other tasks assigned from time to time by superior.
Benefit
Salary range: RM3,500 - RM5,000
<Leaves>
• AL:14days/year
• ML:14days/year
<Allowances>
• Transportation: RM200/month
• Phone: RM200/month
<Misc.>
• Annual bonus (depending on company and individual performance)
• Free office parking
• Medical for dependents RM2,000/year
*Other benefits will be shared in more detail during interview sessionDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment