27个职位: Manufacturing(Computer/Telecommunication)

Sales Engineer (Building Automation)ID:60281
3,500 MYR ~ 5,000 MYRSeputeh
工作内容
• Responsible for the sales & marketing of products, system and solution.• Response to all sales enquiries and prepare for the quotation and tender documents.• Responsible for meeting customer requirements through service deliveries, establishing customers and identifying potential business opportunities.• Develop and maintain good relationships with new and existing customers, end users, M&E consultants and contractors. • Responsible to meet yearly target to achieve KPI.• Timely report to superior for the sales activities. • Update customers on company’s new products regularly and obtain their feedback.• Prepare sales reports, presentation, proposal material and update job list.• Update and submit weekly report.• Responsible to follow up payment and collection with customers and update to Finance from time to time.• Ensure customer information to be kept confidentially and adequately according to company rules and regulations.• Work with engineering team to ensure after-sales service to customer, providing expert advice / consultancy, strengthening customer relationship, etc.• Work closely and maintain good communication within department and other departments. • Maintain compliance with all company policies and procedures.• Responsible for any other tasks assigned from time to time by superior.
福利制度
Salary range: RM3,500 - RM5,000

<Leaves>
• AL:14days/year
• ML:14days/year

<Allowances>
• Transportation: RM200/month
• Phone: RM200/month

<Misc.>
• Annual bonus (depending on company and individual performance)
• Free office parking
• Medical for dependents RM2,000/year

*Other benefits will be shared in more detail during interview session
DFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
工作内容
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Physical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Chief Financial Officer (CFO)ID:59799
15,000 MYR ~ 25,000 MYRCheras (KL)
工作内容
■Accounting & Financial Governance- Ensure integrity and accuracy of all financial records, accounting policies, and group-wide financial reporting- Oversee monthly, quarterly, and annual closing processes, ensuring timely and compliant financial statements- Lead the preparation of consolidated financial statements in collaboration with external accounting firms and auditors- Review and approve financial reports, including income statements, balance sheets, and cash flow statements for board and shareholder reporting- Ensure full compliance with applicable tax regulations, including corporate income tax, withholding tax, and indirect taxes (e.g., SST/GST where applicable)- Oversee tax reporting, filings, and audit processes, ensuring accuracy and regulatory compliance across jurisdictions- Strengthen internal controls, risk management frameworks, and governance structures to prevent fraud and ensure financial integrity- Act as the final escalation point for accounting matters and reporting to the Board of Directors■Corporate Finance & Strategic Financial Management- Lead corporate financial strategy, including long-term value creation, capital allocation, and financial sustainability planningConduct ROI evaluation and financial feasibility analysis for strategic initiatives, investments, and expansion projects- Develop and own 3–5 year financial forecasts, group-level budgeting, and strategic financial planning- Lead capital raising activities, including debt financing, equity fundraising, and structured financing to support business growth- Manage relationships with key financial stakeholders, including investors, banks, private equity, and venture capital firms- Oversee investor relations, including communication, reporting, and management of data rooms and due diligence processes- Lead negotiation of financing terms, credit facilities, covenants, and investment structures- Optimize group structure and capital structure to improve tax efficiency, profitability, and IPO readiness- Provide strategic oversight on mergers and acquisitions, joint ventures, and market expansion opportunities- Advise the CEO and Board on financial strategy, investment decisions, risk exposure, and corporate transformation initiatives- Monitor business performance metrics, including ROI and IRR, ensuring alignment with long-term strategic objectives- Drive financial digital transformation initiatives, including ERP implementation and data-driven financial planning systems
福利制度
- EPF(11%), SOCSO provided
- Bonus(Depends on the Performance - 2months in 2024)
- Transportation Allowance(Maximum RM200)
LRT/MRT = public total fare
Motorcycle = RM0.45/km
Car = RM0.70/km

AL:
14 days (0 to 1 year),
16 days (1 to 4 year)
18 days (After 4 year)

MC:
14 days (0 to 2 year)
16 days (3 to 4 year)
18 days (After 4 years)

Medical Claims: RM1,000 per year
Insurance :
AXA Affin (Group Hospitalization & Personal Accident)

Others :
- Annual Medical Checkup (Leader and Above)
- Annual Medical Checkup (Staff work more than 1 year and aged above 30 years)
- Housing Allowance
- Education Benefits
- Medical Life and Accident Insurance for all staff
- Position Allowance (Instructor and Leader)
- Birth Allowance
- Marriage Allowance
- Loyalty Award
- Cleaning and Good Attendance Award
- Team Entertainment Allowance
- Bereavement Allowance
- Field Visit Allowance
- Accommodation Allowance (for Visit)
Logic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru
工作内容
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Head of Department (Accounting)ID:59493
11,500 MYR ~ 17,000 MYRCheras (KL)
工作内容
・Check if the bookkeeping and ledgers are accurate・Check daily transaction, pretty cash timely.・Collaborate with an accounting firm for financial statement preparation・Prepare financial statements such as income statements, balance sheets, and cash flow statements for presentation to management and shareholders.・Prepare and submit tax returns, calculate taxes accurately・Support to create financial plans for the future by forecasting income and expenses.・Audit internal financial processes and transactions to prevent fraud.・Coordinate with external auditing firms to report accounting.・Reporting to Director
福利制度
- EPF(11%), SOCSO provided
- Bonus(Depends on the Performance - 2months in 2024)
- Transportation Allowance(Maximum RM200)
LRT/MRT = public total fare
Motorcycle = RM0.45/km
Car = RM0.70/km

AL:
14 days (0 to 1 year),
16 days (1 to 4 year)
18 days (After 4 year)

MC:
14 days (0 to 2 year)
16 days (3 to 4 year)
18 days (After 4 years)

Medical Claims: RM1,000 per year
Insurance :
AXA Affin (Group Hospitalization & Personal Accident)

Others :
- Annual Medical Checkup (Leader and Above)
- Annual Medical Checkup (Staff work more than 1 year and aged above 30 years)
- Housing Allowance
- Education Benefits
- Medical Life and Accident Insurance for all staff
- Position Allowance (Instructor and Leader)
- Birth Allowance
- Marriage Allowance
- Loyalty Award
- Cleaning and Good Attendance Award
- Team Entertainment Allowance
- Bereavement Allowance
- Field Visit Allowance
- Accommodation Allowance (for Visit)
Senior Technical EngineerID:60114
6,000 MYR ~ 7,000 MYRSimpang Ampat
工作内容
• Machine assembly, standard part and fabrication part receiving, modifcation, alignment, test run, trouble shooting, installation and customer service as define by department Standard Operating Procedure (SOP), Work Instruction (WI) and Customer Specification. • Perform fine tuning, troubleshooting and analyze machine performance related issues followed by initiating rework or changes required.• Lead, support and coordinate with project team to resolve machine performance issues which is not able to solve by Production team within the allocated deadline/ budget/ quality for each project he is assigned including extra hours as needed. • Feedback and update on time to Production Manager/Mechanical Assembly Manager/Project Manager on project progress and issue encounters as define by Standard Operating Procedure (SOP) and Work Instruction (WI). • Records any information discovered during the fine tuning process that would make the process easier and more efficient; Production Improvement Activity. • Assist Production Manager/Mechanical Assembly Manager on section planning and lead improvement activities. • Develop training program and conduct training for production staffs including subcontractors. • Analyzes assembly blueprint and specification manual (for Build To Print) • Responsible for the use of production facilities and individual tools or equipment as define by Company Tools - Term and Condition. (5%) • Follows safety rules and keeps work area clean and organized as define by 5S Best Practice. • Performs other duties and assignments as instructed by superior from time to time.
福利制度
Salary range: RM6,000 - RM7,000

Fixed allowances:
• Phone allowance
• Petrol allowance

AL: Start with 14 days
SL: 14 / 18 / 22 days

<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance

<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis

<If travelling>
• Daily allowance (Depending on the country they visit)
Memory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Standard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Custom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment