27个职位: Manufacturing(Computer/Telecommunication)
Principal Engineer/Principal Architect (Design Verification)ID:59120
20,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced and visionary Principal Engineer/Architect (Design Verification) to lead and drive next-generation design verification strategies, methodologies and execution. The ideal candidate will play a key technical role in shaping DV architecture, methodologies, and execution frameworks to ensure world-class product quality and verification efficiency.Join us if you are a passionate and forward-thinking verification leader who thrives in a fast-paced, innovation-driven semiconductor environment and enjoys mentoring teams, solving complex verification challenges, and influencing design quality and other global engineering teams.Key Responsibilities1. DV Architecture and Methodology Leadership• Define and drive scalable, reusable, and high-efficiency DV architecture and methodology.• Establish verification best practices, including testbench architecture, constrained-random verification, coverage-driven methodologies, and formal verification integration.• Champion automation, regression management, and coverage closure frameworks for continuous efficiency improvement.2. Technical Strategy and Execution• Define verification strategies and verification plans for complex IP design verification (NOC, memory, etc.).• Evaluate and implement state-of-the-art tools, verification techniques, and verification accelerators.• Drive sign-off criteria definition, including functional and code coverage, assertions, and quality metrics.3. Cross-Functional Team Collaboration• Collaborate closely with architecture, design, software teams to ensure robust verification plans and alignment on design intent.• Provide technical guidance to local and global DV teams to standardize and scale best practices.4. Leadership and Mentoring• Mentor and develop technical talent within the DV team, promoting innovation and continuous learning.• Conduct technical reviews, training, and methodology adoption sessions.• Act as a key technical interface with stakeholders and management on DV efficiency and quality metrics.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCircuit Design Manager / Senior ManagerID:59119
15,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery• Work closely with business development team to understand future projects and resource needed• First line of clarification and explanation for customer related questions and support• Work with post silicon team for design intent and required validations
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPrinciple Digital Design Engineer (Logic)ID:59118
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustomer Service - Cantonese Speaker (Fresh Grads OK)ID:58923
3,700 MYR ~ 4,200 MYRPutrajaya/Cyberjaya, Other KL District工作内容
- Provides an administrative support service to the Managed Services Client Service Desk team.- Provides entry level administrative tasks as required by the team.- Responsible for receiving, validating, and logging client requests, capturing the detail of the request.- Ensures the correct escalation procedure is followed on all critical calls and requests and assists with analyzing and interpreting the request to ensure the correct categorization and prioritization.- Works closely with colleagues to ensure the user is kept updated on the progress in relation to the resolution of the pending tickets / requests.- Ensures all relevant documents related to the tickets / requests are maintained, including the client’s information.- Communicates in a professional manner, provide updates and ensure clients are aware of the actions that are being undertaken on their behalf.- Performs any other related task as required.
福利制度
- Mobile Allowance RM200
- Annual Performance Individual Bonus
- Medical Benefit
- Dental Benefit
- Wellness Benefit
- Annual Leave
- Medical LeaveFront-end Web DeveloperID:58909
6,000 MYR ~ 12,000 MYRBangsar工作内容
Industry: IT, Website design, programming and develpmentRole: Frontend web development Special about this job: You will be in charge of web development using "RCMS" and "Kuroco", which is originally developed CRM system by Deverta. "RCMS" is specialized in simplify the contents management while another system "Kuroco" is specialized in API (Application programming Interface). We will continuously incorporate with the latest technology so you may also need to study & brush up your skills continuously to catch up with it.Also we require all engineers to be performing as a full stack engineer but not only front-end.Below is general job scope:-Develop new user-facing features-Build reusable code and libraries for future use-Ensure the technical feasibility of UI/UX designs-Optimize application for maximum speed and scalability-Assure that all user input is validated before submitting to back-end-Collaborate with other team members and stakeholders
福利制度
Salary; Depend on experience
-Transportation Allowance :RM 350 per month
-Medical Allowance(Claim basis) :RM200 per month (Max)
-Hospitalization (Claim basis) :RM5,000 per month (Max)
-Medical Examination / Special Consultation(Claim basis) :RM350 per month (Max)
-Annual Leave
A) For the first two years of your employment, entitled to 10 days annual leave.
B) At the start of your third (3rd) year serving the company, entitled to 14 days annual leave.
C) At the start of your fifth (5th) year serving the company, entitled to 18 days annual leave.
-Sick Leave: 14 days of paid sick leave a year, required to provide a medical certificate.IP Logic Design Principle EngineerID:58602
20,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The IP Logic Design Principle Engineer will be responsible for architecting microarchitecture design implementation of an IP, spanning across all IP stack such as application layer, transaction layer, link layer, die to die layer, physical layer. Ability to code verilog / system verilog RTL for complex IP, review RTL coding, orchestra IP development phase for projects from beginning to completion. This includes the ability to technically drive the IP team on Design / Validation in completing technical tasks up to IP releases for customers. Candidate must be also capable of solving high speed timing convergence on various processes and collaborate with cross-functional teams to meet project specifications. The role will drive performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Microarchitecture Definitions• Define microarchitecture definition across layers and define a clean inter unit partition requirements.• Drive design team to deliver best-in-class IP design that optimizes for area, latency, power and performance.• Ability to distribute and drive the design team to implement high quality design and meeting time to market requirements.2. IP Design Responsibility• Implement very complicated high-speed design which can converge timing convergence at high frequency.• Capable of orchestrating the team on right directions of timing convergence, CDC, lintra and etc. for tools closure.3. IP Quality Responsibility• Review IP design and validation testplan to make sure IP Design is at top notch quality.4. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
