61 Jobs: IT/Telecommunications
【Japanese Speaker】 Sales Specialist (System Integration)ID:59670
8,000 MYR ~ 10,000 MYRKota Damansara/Petaling JayaJob Description
The ideal candidate will be fluent in English and Japanese with a proven track record in solutions selling within the IT or technology sector. This role involves identifying and engaging with new business opportunities, nurturing client relationships, and achieving sales targets for complex IT solutions across Japanese-Oriented Companies in Malaysia.a. Lead Generation & Prospecting: • Actively identify, research, and qualify new business opportunities and leads for system integration projects in target industries (e.g., Japanese-Oriented Companies) within Malaysia, leveraging fluency in required languages.• Conduct outbound calls and emails outreach in Japanese or English to introduce our SI capabilities and generate interest.• Participate in industry events, technology forums, and networking activities (both virtual and in-person) to expand the professional network and capture leads specific to IT infrastructure, software, and services.b. Solutions Selling & Technical Understanding: • Develop a strong understanding of our core system integration offerings, including but not limited to: > Key Focus Solutions: Own Managed Services (e.g., Firewall Managed Services, IT Help Desk Services, RPAM Service & etc).• Other Solutions: i. Network Infrastructure (e.g., Firewall, LAN/WAN, Wi-Fi, Security solutions).ii. Server & Storage Solutions (e.g., On-premises, Virtualization, Cloud integration).iii. Cybersecurity Solutions (e.g., Endpoint Protection).iv. Cloud Services (e.g., IaaS, PaaS, SaaS integration, Hybrid Cloud).• Conduct compelling presentations and demonstrations tailored to the specific IT requirements and business challenges of clients, utilizing both languages effectively.• Collaborate closely with project team, vendor to understand client's existing IT environments and propose optimal, integrated solutions.• Understand customer requirements, pain points, and objectives to propose suitable and scalable IT solutions.c. Sales Cycle Management: • Prepare and present comprehensive proposals, quotation, and contracts in the client's preferred language (Japanese or English, often a blend).• Negotiate terms and close sales deals for complex IT projects to meet or exceed monthly, quarterly, and annual sales targets.• Manage the entire sales pipeline from lead generation to post-sale follow-up, ensuring smooth project handover to the delivery team.d. Client Relationship Management: • Build and maintain strong, long-lasting relationships with new and existing clients in both the private and public sectors through proactive communication and exceptional service.• Act as a primary point of contact for clients, addressing IT-related inquiries, resolving issues, and ensuring customer satisfaction throughout the project lifecycle in their preferred language.• Identify opportunities for upselling and cross-selling additional IT services, hardware, and software within the existing client base.• Gather client feedback and market intelligence specific to IT needs and challenges in the Malaysian market to contribute to solution development and sales strategy.e. Market Intelligence & Strategy: • Stay informed about IT industry trends, emerging technologies, market conditions, and competitor offerings within the Japanese-Oriented Companies system integration landscape.• Provide insights into local business practices, cultural considerations, and communication styles to optimize sales approaches within Malaysia.f. Reporting & Administration: • Maintain accurate and up-to-date client information, sales activities, and project statuses in organized format.• Generate regular sales reports, forecasts, and pipeline analyses specific to IT projects.• Manage & collaborate administrative tasks related to sales orders, solution contracts, and invoicing with finance team.
Benefit
- Employment: Permanent
- Working place: Petaling Jaya, next to Surian MRT
- Medical expense assistance: Company will support up to RM100/monthSenior Standard Cell Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementProject ManagerID:59617
8,000 MYR ~ 10,000 MYRSeri PetalingJob Description
• Manage the planning, organizing and implementation of complex strategic project/initiatives• Monitor of Project Implementation Plan of overall works• Review progress against plans, reporting progress and result to the Management• Lead and coordinate project team to eliminate the obstacle as well as mentoring the team to improve project approach, process and implementation• Develop and monitoring project plan and track project milestones with appropriate process to ensure the project runs according to schedule and budget• Planning work program of project and monitoring stage completion• Monitoring inspections and test are carried out in accordance to the contract specification• Coordinate, review and submission of progress payment to the customer and facilitate timely certification of sub-contractor claims• To liaise with Client• Co-ordinate interfacing activities works of various sub-contractors• Perform other duties as assigned from time to time
Benefit
1) Annual Leave
(<2 years @ 14 days)
(2-5 years @ 17 days)
(>5 years @ 20 days)
2) Medical Leave
(<2 years @ 14 days)
(2-5 years @ 18 days)
(>5 years @ 22 days)
3) Medical Claims (RM800/year) at panel clinic
4) Dental claim (RM300/year)
5) Insurance (after confirmation)
6) Mobile Phone claim (up to RM120)
7) Mileage, parking & toll claim – for site visit/meeting clientStrategy ManagerID:59478
10,000 MYR ~ 15,000 MYRDamansara HeightsJob Description
SummaryThe role will involve analyzing and providing solutions to businesses problems, as well involvement in overseeing development of the proposed solutions and finally completion of the projects. There will also be participation in executing plans to managing change impacts to our customers’ organization.Key Responsibilities:Business1.Market Research - gathering market information to be used for data analysis and provide analysis & conclusion for market research2.Gather business information to be used for business process improvement analysis and provide assessment, recommendation and conclusion on the analysis.3.Recommend solutions based on analysis, logical thinking and problem-solving skillsProjects1.Assist in formulating and execute project governance, monitors and controls.2.Assist in formulating project tracking and execute progress monitoring.3.Will be project knowledge source of reference for the project team.4.Coordinating and streamlining all activities within a project.Change1.Execute plans in managing people and organization changes.2.Involved in planning and executing communication, trainings, and stakeholder management.3.Lead the support and alignment to project activities.
Benefit
・AL: 16d
・MC: 22d
・Handphone Allowance = RM 50
・Medical Claim: Single RM 1,800, Married RM 2,250
・Hospitalization Leave = 60d
・Hospitalization Claim: up to RM 60k
・Season Parking: Paid on monthly reimbursement basis
・Fitness Allowance: Claimable up to RM 360 per quarter or RM 120 monthly
・Dental, Optical claim
・Regular Company Events: Sports Tournament, Outdoor Activities
・Bonus based on company and individual performance
・Access to fitness, dental, and optical benefits.
・Regular company events, including sports tournaments and community activities.Circuit Design Engineer (Senior/Staff/Principle)ID:59444
6,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Senior/Staff• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.Principle• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery.• Work closely with business development team to understand future projects and resource needed.• First line of clarification and explanation for customer related questions and support.• Work with post silicon team for design intent and required validations.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCrypto Quant Researcher (Strategy Builder)ID:59315
13,000 MYR ~ 16,000 MYRBukit Bintang/KLCCJob Description
About UsWe are building a next gen quantitative trading and research platform focused on systematic, data driven alpha generation across crypto markets. This is not a signal copying or indicator tuning role we want people who design, test, break, and rebuild their own strategies from first principlesRole OverviewYou will research, design, backtest, and iterate original crypto trading strategies across spot, perpetuals, and derivatives. You will work closely with engineering and trading to convert ideas into production ready systems.Key Responsibilities- Design original crypto trading strategies (momentum, mean reversion, market structure, volatility, funding, microstructure, etc.)- Build and maintain backtesting pipelines using historical crypto data (tick, OHLCV, funding, order book if available)- Perform rigorous statistical evaluation (drawdowns, regime behavior, robustness, overfitting checks)- Iterate strategies based on failure analy sis, not curve fitting- Research and engineer custom features/factors beyond standard indicators- Document strategy logic, assumptions, and failure modes clearly- Collaborate with engineers to move research into live trading systems
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Performance bonus
Other benefits will be further disclosed if shortlistedDesign Verification Engineer (Senior/Staff/Principal)ID:59121
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a highly experienced and technically profound Design Verification Engineer. This role will be responsible for RTL verification, debug, functional coverage and SVA assertion development, UVM testbench development, testplan development and new verification methodology.Key Responsibilities- Develop and maintain UVM-based verification environments for IP designs.- Create detailed test plans based on design specifications, architectural documents, and use-case scenarios.- Implement constrained-random testbenches, scoreboards, and monitors to validate functional behavior.- Perform coverage-driven verification, including:a. Functional coverage (covergroups, coverpoints)b. Code coverage (statement, branch, toggle)c. Assertion coverage (SystemVerilog assertions)- Drive coverage closure by identifying gaps and enhancing test scenarios.- Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis.- Apply Formal Property Verification (FPV) to prove critical design properties and uncover corner-case bugs.- Debug simulation failures and collaborate with RTL designers to resolve issues efficiently.- Document verification results, coverage metrics, and regression summaries for traceability and quality assurance.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment