Overview

• Salary

  8,000 MYR ~ 35,000 MYR

• Industry

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• Job Description

  Position Overview
  We are seeking RTL Design Engineers at Junior/Intermediate and Senior levels to join our Hardware Engineering team, focusing on ASIC and SoC design.
  
  The successful candidates will be responsible for RTL development, functional verification, simulation, debugging and design quality throughout the front-end design flow. Depending on experience and seniority, the role will involve implementing well-defined RTL blocks under guidance or independently owning RTL blocks from specification through verification closure and sign-off.
  
  Key Responsibilities
  A. RTL Design & Development
  - Develop synthesizable RTL using Verilog and/or SystemVerilog in accordance with design specifications and team coding guidelines.
  - Implement and maintain RTL blocks for ASIC and SoC designs, ensuring functionality, code quality and design efficiency.
  - Apply synchronous design principles, including clocking, reset strategies, data valid/ready handshaking and clock domain crossing (CDC) techniques.
  - Design and maintain functional blocks such as finite state machines (FSMs), FIFOs, arbiters, register files, control logic and data paths.
  - Work with standard bus protocols, including APB and AHB-Lite, with awareness of AXI4.
  - Consider area, power and performance (PPA) implications when developing and optimizing RTL.
  - Collaborate with design, verification, physical design (PD), DFT and other cross-functional teams to resolve design issues and improve implementation quality.
  
  Junior / Intermediate Level
  - Implement well-defined RTL blocks based on detailed microarchitecture specifications under the guidance of senior engineers or technical leads.
  - Develop foundational knowledge of RTL design methodologies, synthesis implications, CDC concepts and low-power design techniques.
  - Participate in design reviews, identify potential corner cases and proactively raise technical questions or design concerns.
  - Improve RTL quality and design efficiency based on code review feedback.
  
  Senior Level
  - Independently own RTL blocks from specification review and design implementation through verification closure and sign-off.
  - Contribute to microarchitecture definition, design specification documentation and technical design reviews.
  - Optimize RTL for timing closure, area and power through techniques such as pipelining, retiming and appropriate coding strategies.
  - Implement and evaluate low-power design techniques, including clock gating, isolation cells and retention flops.
  - Resolve complex RTL design issues and work with physical design teams to address timing and place-and-route feedback.
  - Provide technical guidance and informal mentoring to junior engineers.
  
  B. Functional Verification & Simulation
  - Develop and execute directed and self-checking SystemVerilog testbenches to verify RTL functionality.
  - Run simulations, debug functional failures and analyze waveforms using industry-standard tools.
  - Write SystemVerilog Assertions (SVA) to capture design intent and verify key interface requirements.
  - Apply functional coverage concepts to assess verification completeness and identify potential coverage gaps.
  - Collaborate with design verification engineers to investigate issues and ensure design quality.
  
  Junior / Intermediate Level
  - Develop directed testbenches for assigned RTL blocks and execute simulations using tools such as Synopsys VCS, Questa or Icarus Verilog.
  - Perform waveform debugging using Verdi, DVE or equivalent tools.
  - Demonstrate basic understanding of UVM concepts, including agents, sequences and scoreboards.
  - Add basic functional coverage points and develop familiarity with assertions and verification methodologies.
  
  Senior Level
  - Develop and debug more comprehensive testbenches and contribute to UVM agents, sequences and verification environments.
  - Interpret coverage reports and drive functional coverage closure in collaboration with verification teams.
  - Apply assertions, assumptions and cover properties, with exposure to formal verification methodologies.
  - Investigate complex simulation failures and contribute to root-cause analysis across RTL, verification and integration issues.
  
  C. Design Quality, Sign-Off & Integration
  - Ensure RTL designs comply with applicable design specifications, coding standards and quality requirements.
  - Review simulation results, lint reports and timing information to identify and resolve potential design issues.
  - Understand the impact of RTL changes on synthesis, timing, integration and downstream implementation.
  - Collaborate with verification, DFT and physical design teams throughout the design lifecycle.
  
  Junior / Intermediate Level
  - Develop an understanding of static timing analysis (STA), including setup and hold violations.
  - Resolve common lint warnings and develop familiarity with CDC analysis and synchronizer insertion.
  - Understand basic DFT concepts, including scan chains and test modes.
  - Support design reviews and sign-off activities under senior engineer guidance.
  
  Senior Level
  - Interpret STA reports, timing slack and critical paths, and implement RTL changes to address timing issues.
  - Resolve common CDC and reset domain crossing (RDC) violations and lint issues.
  - Apply DFT awareness when designing RTL and supporting scan insertion and test mode requirements.
  - Work closely with physical design teams to resolve implementation-related issues and support design sign-off.
  - Take ownership of RTL quality and verification closure for assigned blocks.
  
  D. Scripting, Automation & Design Tools
  - Use scripting languages and automation tools to improve design, simulation and debugging efficiency.
  - Work with existing simulation flows, tool scripts, file lists and build configurations.
  - Analyze simulation logs and support the maintenance of design and verification workflows.
  
  Junior / Intermediate Level
  - Write basic Python, Tcl or shell scripts to automate repetitive simulation tasks.
  - Edit existing Makefiles and Tcl run scripts and parse simulation logs.
  - Demonstrate proficiency in at least one industry-standard simulation tool.
  
  Senior Level
  - Develop and maintain Python, Tcl or shell scripts for simulation automation, regression execution and log analysis.
  - Manage file lists, hierarchy extraction and simulation flow configurations.
  - Troubleshoot tool-flow issues and improve automation efficiency where appropriate.
  - Utilize synthesis and formal verification tools as required by the project.
  
  E. Technical Collaboration & Continuous Improvement
  - Collaborate with cross-functional engineering teams to support successful ASIC/SoC design implementation.
  - Participate in design reviews, technical discussions and knowledge-sharing activities.
  - Maintain clear design documentation and communicate technical issues, progress and blockers effectively.
  - Continuously improve technical knowledge of RTL design, verification methodologies and EDA tools.
  
  Junior / Intermediate Level
  - Work collaboratively within an established design team, seek clarification when requirements are unclear and incorporate feedback from senior engineers.
  - Provide timely progress updates and proactively communicate design issues or blockers.
  
  Senior Level
  - Drive technical discussions for assigned RTL blocks and document design decisions and implementation considerations.
  - Coordinate closely with design verification, DFT, physical design and software teams to resolve technical issues.
  - Mentor junior engineers and contribute to improving team design practices.