Sr Memory Circuit Design EngineerID:59447

10,000 MYR ~ 22,000 MYRBayan Lepasabout 17 hours ago

Overview

  • Salary

    10,000 MYR ~ 22,000 MYR

  • Industry

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • Job Description

    We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.

    Key Responsibilities
    • Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery).
    • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.
    • Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.
    • Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.
    • Create concise margin/performance reports & track design closure metrics.
    • Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.
    • Work with Design Automation/Software Team/EDA vendor
    • To integrate Memory circuits into Memory Compiler system
    • To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)
    • Support silicon bring-up, characterization and simulation-to-silicon correlation.

Qualifications

  • Requirement

    • BS/MS in Electrical/Electronic Engineering (or equivalent experience).
    • 4-10+ years of memory circuit design experience (SRAM and/or RF).
    • Strong CMOS device fundamentals & deep submicron effects impacting low-voltage memories.
    • Hands-on with Cadence Virtuoso and SPICE simulators (Spectre/HSPICE or equivalent) and waveform debug.
    • Experience with variability-aware design: PVT corners, Monte Carlo, margining and yield analysis.
    • Understanding of physical implementation and sign-off (DRC/LVS, extraction, EM/IR) and layout impact on circuits.
    • Experience with memory characterization and model generation flows.
    • Experience in using Memory Compiler from any Foundry or EDA vendor.

    Preferred / Nice-to-Have Experience
    • Experience in integrating Memory circuits into Memory Compiler software.
    • Working knowledge of RTL/Verilog modeling and memory macro integration/DFT needs.

  • English Level

    -

  • Other Language

    English

Additional Information

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