58个职位: 峇六拜 Bayan Lepas最新招聘信息
Senior/Staff Design for Testability (DFT) EngineerID:59731
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced and strategic Senior or Staff DFT Design Engineer to join our team and in support the company’s ASIC design and IP development initiatives in the area of Design for Testability (DFT) design and verification. The candidate will play a key role in leading the planning and execution of various DFT features implementation and verification.Key Responsibilities:• DFT microarchitecture planning, DFT rtl generation/integration and verification of various DFT feature.• Memory BIST design implementation and verification for IP and ASIC projects.o Mbist logic insertion, integration and verification.o Mbist collateral generations including mbist pattern and timing constraint.• Scan design implementation and verification for IP and custom ASIC.o Scan controller generation (clock/reset control, test compression) implementation and scan chain stitchingo ATPG pattern generations and GLS simulation to verify the scan design.o Scan collaterals generation including scan constraint, scan timing closure, ATPG pattern debug etc.• JTAG/Boundary Scan design implementation and verificationo Tap controller design and verificationo Boundary scan chain implementation at IP and soc level, bscan verification and bsdl generation.• Post silicon debug and test pattern bring up supports to enable silicon power on activities and high-volume manufacturing testing.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Staff Digital Design EngineerID:59719
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementFinance DirectorID:59724
20,000 MYR ~ 35,000 MYRBayan Lepas工作内容
Job descriptionThe Finance Director will be in the lead together with the other members in the Management Team for company new phase to control further growth. The role includes financial and business controlling to improve working capital, cashflow and profitability for various operational units.Key duties and responsibilities• Drives the current financial team(s) in performing/reviewing the monthly reporting and compile the required deliverables under the company accounting standards based on MPERS.• Drives the further development of the business control function in order to share the outcomes with the Management Team(s) to monitor and take actions to improve the KPI's.• Seniority to support the Management Team(s) and Managing Director Asia.• Drives and supports the critical operations processes to secure the committed output/financial plan.• Develop further strong focus on working capital, cashflow and cost management.• Prepare analysis on capital project investments and other business proposals. Ensure sound business case and realistic cost/benefit analyses are made against new opportunities and initiatives.• Ensure further automation in (financial) processes and take responsibility and actions on the required attention points.• Embed and secure group-wide way of working.• Drives the financial year-end closing and support financial audits.• Coordination of the budget- and forecasting processes.• Monthly analysis
福利制度
- 13 months salary
- Performance Bonus (Average 2 months)
- Transport allowance
- Medical Claim
- Optical/ Dental Claim
- Annual Leave – 14 days
- Life insurance and HospitalizationSenior Staff Advanced Package & Board TeamID:59718
15,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior Staff Advanced Package & Board Team will lead the design, development, and implementation of advanced IC packaging and board-level solutions that enable high-performance, cost-effective, and reliable silicon products. This role requires strong technical leadership across multiple engineering domains — including substrate/interposer design, board design, SI/PI/thermal analysis, and manufacturing interface — while driving cross-functional collaboration with silicon design, system architecture, and OSAT/EMS partners.The successful candidate will define and execute the company’s packaging and board technology roadmap to support next-generation chiplet-based architectures, 2.5D/3D integration, and heterogeneous systems.Key Responsibilities1. Leadership & Strategy• Lead the Advanced Package & Board Design Team, including substrate, interposer, and PCB design engineers.• Define and execute packaging and board technology strategy aligned with company silicon product roadmap.• Establish design and verification methodologies for advanced packaging (e.g., 2.5D, fan-out, chiplet integration).• Drive innovation in thermal management, signal integrity, and power delivery optimization.2. Technical Execution• Oversee design and validation of interposers, substrates, and system boards from concept to production release.• Guide integration of chiplets, HBM, and passive components using state-of-the-art packaging technologies.• Ensure robust SI/PI, mechanical, and thermal analysis for design sign-off.• Collaborate with silicon design teams on bump assignment, die floorplanning, and package co-design.• Manage board-level design for system bring-up, test platforms, and reference designs.3. Supplier & Ecosystem Management• Engage and qualify OSATs, substrate vendors, and PCB manufacturers to ensure quality and yield.• Partner with EDA vendors to establish design automation flow and DRC verification.• Drive technology transfer and pilot runs with manufacturing partners.4. Project & People Management• Plan resources, schedules, and budgets to ensure timely delivery of packaging and board design projects.• Build and mentor a high-performing team with expertise across electrical, mechanical, and materials engineering.• Foster collaboration across silicon, test, reliability, and operations teams.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment[ Penang ] Telemarketer / Inside Sales Executive (12-months Contract - Renewable)ID:58883
2,800 MYR ~ 3,100 MYRBayan Lepas工作内容
・Deliver prepared sales talks, reading from scripts that describe products in order to persuade potential customers to know more about our products and schedule appointments for sales representative to meet with prospective customers.・Explain products and answer questions from customers.・Obtain customer information such as name, address and enter information into computers.・Adjust sales scripts to better target the needs and interests of specific individuals.・Learn up product information and knowledge.
福利制度
・Basic Salary = RM 2,500 ~ RM 2,800
・Fixed Car Allowance = RM 300
・Monthly Incentive Scheme up to RM700 (After individually handle project)
・Annual Leave : 12 Days per contract
・Sick Leave: 14 Days
・Half Yearly Bonus
・13th Month Bonus available upon contract renewal
・Claimable Overtime fee
・Parking Subsidy
・Dental / Optical / Health Screening Claimable RM500
・Training provided[ Penang ] Consulting Sales EngineerID:58162
4,700 MYR ~ 5,200 MYRBayan Lepas工作内容
•Promoting and offering consultancy services with Keyence product related to Quality assurance/Quality control, Production Engineering, Research and Development field in various manufacturing industries.•Working in full sales cycle: discover, develop, propose, negotiate, and closing•Actively promoting our products over the phone to qualify customers before appointments.•Visiting potential customers and performing product demonstration to end user directly.•Through asking customers’ operation and application testing, proving our solution and persuading customers to purchase our products.•Managing certain product-line sales in the assigned territory.•Reviewing and analyzing your own sales performance, aiming to meet or exceed targets sustainably.•Attending team meetings and training session with colleagues to improve sales skill &technical knowledge on product applications.
福利制度
・Basic Salary = RM 3,500 ~ RM 4,000
・Fixed Car Allowance = RM 1,200 (upon joining, during probation period)
・Fixed Increment of RM 700 after probation
・Monthly Incentive System (After Probation)
・Annual Leave : 14 Days (pro-rated based on joining date)
・Sick Leave: 14 Days
・Insurance provided: GTL. GHS, GPA
・Medical, Optical, Dental & Other Flexi Benefits: RM7000
・EPF Employer Contribution at 15%
・Half Yearly Bonus
・Weekly Fruits Day
・Annual Dinner
・Parking provided by CompanySr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr eFUSE Design EngineerID:59655
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an eFUSE Design Engineer to own the end-to-end development of production-grade eFUSE IP on leading-edge process nodes. You will drive eFUSE array architecture, circuit design, full simulation-based verification, collateral and view generation, and quality checks — delivering robust, sign-off-ready eFUSE IP to downstream SoC integration flows. Bitcell-level design knowledge is valued; direct bitcell design experience is a plus but not required. Seniority level to be determined by experience.Key Responsibilities• Design and architect the eFUSE array circuit, including sense amplifier, reference bias, programming current control, address decoder, column multiplexer, and repair logic; ensure correct functional operation across all PVT corners.• Develop and execute comprehensive simulation plans for the eFUSE macro, covering DC/AC characterization, programming/read margin analysis, retention, endurance, and reliability corner simulations (MC, Mismatch, Aging); validate against product specifications and foundry bitcell models.• Generate and validate all required IP deliverable views and collateral: timing models (Liberty .lib), physical abstracts (LEF/GDS), behavioral models (Verilog), datasheets, and application notes; ensure consistency across all views and compliance with delivery checklist.• Define and execute IP quality checks (QC) and quality assurance (QA) regression suites; run DRC/LVS/ERC/PEX sign-off on the eFUSE macro layout; conduct formal and simulation-based functional verification; ensure all sign-off criteria are met prior to IP release.• Collaborate with the foundry and PDK team on eFUSE bitcell characterization data, SPICE models, and process design rules; translate foundry bitcell specifications and reliability requirements into array-level design constraints.• Support Testchip integration of the eFUSE macro, including test circuit design, programming and read test plan development; assist in hardware bring-up, failure analysis, and silicon–to–simulation correlation.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (General Purpose I/O) (GPIO)ID:59654
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.Key Responsibilities• Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).• Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.• Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).• Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.• Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.• Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
