63个职位: 招聘信息 工程师(IT/互联网/电信)
Standard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Analog Mixed-Signal Design)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru工作内容
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Highspeed IO Buffer LPDDR6)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Software Engineer (PLC) ID:60017
6,000 MYR ~ 8,500 MYRBayan Baru工作内容
• Design, development, and implementation of PLC and/or PC based software solutions• Perform system integration, testing and commissioning of advanced control systems for equipment automation system.• Participate in control system requirement analysis.• Involved in drafting of functional specifications and detailed design specification.• Provide technical onsite support to external and internal customers.• Interpret client requirements, identify design parameters, and ensure solutions are implemented accurately and within budget to meet project requirements and schedules• Ensure software issues are resolved in a timely manner
福利制度
Salary package: ~RM5,000 - RM7,000
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview sessionSIPI Engineer (Senior/Staff/Principal)ID:59941
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Job SummaryResponsible for Signal Integrity and Power Integrity (SI/PI) analysis, simulation, lab validation, and customer support for high-speed digital interfaces across chip, package, and board levels.Key ResponsibilitiesSignal Integrity• Simulation for high-speed interfaces: HBM, DDR, LPDDR, UCIe, MIPI• Crosstalk, reflection, impedance, and eye-diagram analysis• Transmission line modeling and stackup reviewPower Integrity• Power delivery network (PDN) analysis and optimization• Decoupling capacitor selection and validation• PDN impedance measurement and simulation correlationTools & Methods• SI/PI tools: HyperLynx, Ansys SIwave, Cadence Sigrity• Lab equipment: TDR, VNA, high-speed oscilloscope• S-parameter, Y/Z-parameter and multi-port matrix analysis Collaboration• Work with chip, package, PCB design, and layout teams• Support customers on board design reviews and technical queries• Participate in design reviews, failure analysis, and root-cause debugging
福利制度
- Annual Leave 14 days
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementAutomation Engineer (Python | Web & Mobile)ID:59976
6,000 MYR ~ 10,000 MYRCheras (KL), Cheras (Selangor)工作内容
Role OverviewWe are looking for a highly capable Automation Engineer with deep expertise in Python and cross-platform automation (Web + Android). This role involves designing, building, and maintaining scalable automation systems with strong emphasis on reliability, system architecture, and production stability.Candidates must be able to independently deliver complete automation solutions and demonstrate prior projects.Key Responsibilities1. Cross-Platform Automation Development• Develop automation systems using:o Python 3.xo Playwright (preferred) or Seleniumo Appium (UiAutomator2)• Handle complex UI flows across web portals and Android apps.• Optimize browser contexts for high stability and success rates.2. Mobile Infrastructure Management• Manage Android devices via ADB.• Orchestrate multi-device environments (UDID).• Automate APK deployment and lifecycle management.• Monitor device activity and process stability.3. System Architecture & Reliability• Design self-healing automation services.• Implement logging, resource management, and service monitoring.• Ensure long-term system resilience and performance.4. API & Real-Time Integration• Integrate RESTful APIs and WebSocket communication.• Validate and test APIs using tools such as Postman.• Coordinate workflows across services.5. DevOps & Environment Management• Maintain Git-based workflows.• Build CLI-based orchestration tools.• Support containerized or VM-based automation clusters.
福利制度
- Allowance RM250/month
- Dental and Optical claim (upon confirmation)
- Company Insurance
- Sport Membership
- Medical Coverage
- AL 14 days
- Medical Leave 14 days
- Hospitalization
- Compassionate Leave
- Marriage Leave
- Maternity and Paternity Leave
- 13 months bonus and performance bonusBackend Developer (C# | .NET | API Systems)ID:59975
6,000 MYR ~ 10,000 MYRCheras (KL), Cheras (Selangor)工作内容
Role OverviewWe are looking for a strong Backend Engineer with proven experience building and maintaining production backend systems using ASP.NET Core within the .NET ecosystem.This role involves taking ownership of an existing API platform, improving its structure, performance, and reliability. The current system was developed rapidly and requires refactoring, architectural improvements, and stricter engineering practices.We expect candidates who can:• Understand and refactor complex backend code• Design scalable APIs• Identify architectural problems and propose solutions• Deliver production-grade backend services with minimal supervisionYou will work closely with frontend engineers and product stakeholders to build stable, secure, and maintainable backend systems.Key Responsibilities1. Backend System Development & Code QualityDesign, develop, and maintain backend APIs using:• C#• ASP.NET Core• Modern .NET runtimeResponsibilities include:• Writing clean, maintainable, and testable backend code• Refactoring poorly structured or legacy code• Enforcing consistent project structure and coding standards• Implementing proper layered architecture (Controllers, Services, Data Access)Candidates must be comfortable working with existing systems and improving them, not just building greenfield projects.2. API Architecture & System DesignDesign and implement robust RESTful APIs to support web applications and external integrations.Responsibilities include:• Designing clear API contracts and data models• Implementing proper validation and error handling• Designing maintainable service layers• Supporting future scalability and feature growthCandidates should demonstrate solid backend architecture thinking, not just endpoint implementation.3. Data Access & Database PerformanceDesign and maintain efficient database interactions using:• Entity Framework Core• Microsoft SQL Server or other relational databasesResponsibilities include:• Writing efficient queries and understanding query performance• Managing schema migrations and database structure• Preventing performance issues such as N+1 queries• Ensuring data consistency and integrityStrong candidates should understand how backend code impacts database performance.4. Performance & ReliabilityImprove backend performance and reliability across services.Responsibilities include:• Implementing asynchronous processing• Reducing unnecessary database calls• Identifying performance bottlenecks• Ensuring APIs remain stable under real-world loadCandidates should demonstrate the ability to diagnose and fix backend performance issues.5. Security & Backend Best PracticesFollow secure backend development practices.Responsibilities include:• Implementing authentication and authorization mechanisms• Protecting APIs from common vulnerabilities• Implementing proper input validation and error handling• Ensuring sensitive data is handled securelyBackend developers must understand that security is enforced on the server side, not the client.6. Engineering Ownership & CollaborationWork closely with engineers and stakeholders to improve the overall system.Responsibilities include:• Participating in code reviews• Contributing to technical decisions• Improving development practices and architecture• Taking ownership of backend quality and maintainabilityWe expect engineers who actively improve systems, not just complete assigned tasks.
福利制度
- Allowance RM250/month
- Dental and Optical claim (upon confirmation)
- Company Insurance
- Sport Membership
- Medical Coverage
- AL 14 days
- Medical Leave 14 days
- Hospitalization
- Compassionate Leave
- Marriage Leave
- Maternity and Paternity Leave
- 13 months bonus and performance bonusFrontend Developer (React | Web Application)ID:59974
6,000 MYR ~ 10,000 MYRCheras (KL), Cheras (Selangor)工作内容
Role OverviewWe are looking for a highly capable Frontend Engineer with strong expertise in React and modern frontend development. This role involves taking ownership of an existing web application, improving code quality, and building scalable, maintainable frontend systems.The current system was rapidly developed and requires restructuring, optimization, and adherence to best practices. Candidates must be able to independently handle frontend architecture, refactor existing code, and deliver production-ready features.Key Responsibilities1. Frontend Development & RefactoringDevelop and maintain frontend systems using:• React• Vite• JavaScript (ES6+) or TypeScriptRefactor and restructure existing codebase for scalability and maintainability.Build reusable components and consistent UI patterns.Implement clean project structure and coding standards.2. API Integration & Data HandlingIntegrate frontend with backend APIs.Handle:• Authentication flows (login, session handling)• Error handling and edge cases• Loading and state managementEnsure proper data flow and avoid frontend-based security risks.3. State Management & ArchitectureImplement and manage application state using:• React hooks• State management libraries (e.g. React Query, Zustand, Redux)Design scalable architecture for growing features.Ensure separation of concerns between UI, logic, and data layers.4. Performance OptimizationOptimize frontend performance and user experience.Implement:• Code splitting and lazy loading• Efficient rendering and memoization• Bundle size optimizationEnsure fast and responsive UI across devices.5. Security & Best PracticesFollow secure frontend practices:• Prevent XSS and unsafe rendering• Avoid exposing sensitive data in frontend• Work with backend to ensure proper authentication and authorizationEnsure frontend does not rely on client-side security assumptions.6. Collaboration & OwnershipWork closely with backend developers and stakeholders.Participate in:• Code reviews• Technical discussions• Feature planningTake ownership of frontend quality and long-term maintainability.
福利制度
- Allowance RM250/month
- Dental and Optical claim (upon confirmation)
- Company Insurance
- Sport Membership
- Medical Coverage
- AL 14 days
- Medical Leave 14 days
- Hospitalization
- Compassionate Leave
- Marriage Leave
- Maternity and Paternity Leave
- 13 months bonus and performance bonus
