概述

• 薪资

  8,000 MYR ~ 16,000 MYR

• 工作行业

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• 工作内容

  We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.
  
  Key Responsibilities
  • Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).
  • Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.
  • Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).
  • Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.
  • Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).
  • Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
  • Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.