概述

• 薪资

  10,000 MYR ~ 30,000 MYR

• 工作行业

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• 工作内容

  We are seeking a highly experienced and technically profound Design Verification Engineer. This role will be responsible for RTL verification, debug, functional coverage and SVA assertion development, UVM testbench development, testplan development and new verification methodology.
  
  Key Responsibilities
  - Develop and maintain UVM-based verification environments for IP designs.
  - Create detailed test plans based on design specifications, architectural documents, and use-case scenarios.
  - Implement constrained-random testbenches, scoreboards, and monitors to validate functional behavior.
  - Perform coverage-driven verification, including:
  a. Functional coverage (covergroups, coverpoints)
  b. Code coverage (statement, branch, toggle)
  c. Assertion coverage (SystemVerilog assertions)
  - Drive coverage closure by identifying gaps and enhancing test scenarios.
  - Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis.
  - Apply Formal Property Verification (FPV) to prove critical design properties and uncover corner-case bugs.
  - Debug simulation failures and collaborate with RTL designers to resolve issues efficiently.
  - Document verification results, coverage metrics, and regression summaries for traceability and quality assurance.